Patents Assigned to SUMITOMO ELECTRIC INDUSTIRES, LTD.
  • Patent number: 12007919
    Abstract: An in-vehicle communication device for transmitting and receiving a signal by a predetermined communication protocol related to Ethernet® (registered trademark), the in-vehicle communication device comprising: a control circuit configured to generate transmission data including interrupt data inserted into an inter-frame gap between Ethernet frames; and a PHY unit having a communication circuit configured to convert the transmission data generated by the control circuit into a signal and transmit the signal.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: June 11, 2024
    Assignees: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industires, Ltd.
    Inventors: Yuanjun Xian, Takeshi Hagihara, Makoto Mashita, Nobuyuki Kobayashi, Takehiro Kawauchi, Tatsuya Izumi, Akihito Iwata, Yusuke Yamamoto
  • Publication number: 20140346530
    Abstract: A semiconductor device according to an embodiment of the present invention includes a SiC substrate, an AlN layer provided on the SiC substrate and having a maximum valley depth Rv of 5 nm or less in an upper surface, a channel layer provided on the AlN layer and composed of a nitride semiconductor, an electron supply layer provided on the channel layer and having a greater band gap than the channel layer, and a gate electrode, a source electrode and a drain electrode provided on the electron supply layer.
    Type: Application
    Filed: May 22, 2014
    Publication date: November 27, 2014
    Applicant: SUMITOMO ELECTRIC INDUSTIRES, LTD.
    Inventors: Ken NAKATA, Keiichi YUI, Hiroyuki ICHIKAWA, Isao MAKABE, Tsuyoshi KOUCHI
  • Publication number: 20140073101
    Abstract: A trench having a side wall and a bottom portion is formed in a silicon carbide substrate. A trench insulating film is formed to cover the bottom portion and the side wall. A silicon film is formed to fill the trench with the trench insulating film being interposed therebetween. The silicon film is etched so as to leave a portion of the silicon film that is disposed on the bottom portion with the trench insulating film being interposed therebetween. The trench insulating film is removed from the side wall. By oxidizing the silicon film, a bottom insulating film is formed. A side wall insulating film is formed on the side wall.
    Type: Application
    Filed: August 2, 2013
    Publication date: March 13, 2014
    Applicant: Sumitomo Electric Industires, Ltd.
    Inventors: Yu Saitoh, Takeyoshi Masuda, Hideki Hayashi
  • Publication number: 20120228613
    Abstract: A method of manufacturing a semiconductor wafer of the present invention includes the steps of: obtaining a composite base by forming a base surface flattening layer having a surface RMS roughness of not more than 1.0 nm on a base; obtaining a composite substrate by attaching a semiconductor crystal layer to a side of the composite base where the base surface flattening layer is located; growing at least one semiconductor layer on the semiconductor crystal layer of the composite substrate; and obtaining the semiconductor wafer including the semiconductor crystal layer and the semiconductor layer by removing the base surface flattening layer by wet etching and thereby separating the semiconductor crystal layer from the base.
    Type: Application
    Filed: May 13, 2011
    Publication date: September 13, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTIRES, LTD.
    Inventors: Yuki SEKI, Issei Satoh, Koji Uematsu, Yoshiyuki Yamamoto
  • Publication number: 20110292955
    Abstract: A tunable LD with reduced number of the butt joint is disclosed. The tunable LD includes the reflector and a waveguide core. The reflector includes a plurality of segments each having a grating region and a space region adjacent to the grating region. The waveguide core includes a gain region extending in two segments adjacent to each other and a tuning region extending in two segments adjacent to each other and also adjacent to the segment for the gain region.
    Type: Application
    Filed: May 25, 2011
    Publication date: December 1, 2011
    Applicant: SUMITOMO ELECTRIC INDUSTIRES, LTD.
    Inventor: Toshimitsu KANEKO
  • Publication number: 20110163323
    Abstract: The method of making a GaN single crystal substrate comprises a mask layer forming step of forming on a GaAs substrate 2 a mask layer 8 having a plurality of opening windows 10 disposed separate from each other; and an epitaxial layer growing step of growing on the mask layer 8 an epitaxial layer 12 made of GaN.
    Type: Application
    Filed: March 11, 2011
    Publication date: July 7, 2011
    Applicant: SUMITOMO ELECTRIC INDUSTIRES, LTD.
    Inventors: Kensaku Motoki, Takuji Okahisa, Naoki Matsumoto
  • Publication number: 20110108853
    Abstract: A compound semiconductor device having reduced contact resistance to an electrode is provided. The compound semiconductor device includes an n-substrate 3 comprising a hexagonal compound semiconductor GaN and having surfaces S1 and S2; an n-electrode 13 formed on the surface S1 of the n-substrate 3; a layered product having an n-cladding layer 5, an active layer 7, a p-cladding layer 9, and a contact layer 11 formed on the surface S2 of the n-substrate 3; and a p-electrode 15 formed on the p-cladding layer 9. The number of N atoms contained on the surface S1 of the n-substrate 3 is more than the number of Ga atoms contained on the surface S1. The electrode formed on the surface S1 is an n-electrode 13. The surface S1 has an oxygen concentration of not more than 5 atomic percent. The number of Ga atoms contained on the surface S3 of the contact layer 11 is more than the number of N atoms contained on the surface S3. The electrode formed on the surface S3 is a p-electrode 15.
    Type: Application
    Filed: July 13, 2010
    Publication date: May 12, 2011
    Applicant: Sumitomo Electric Industires, Ltd.
    Inventors: Masahiro ADACHI, Shinji Tokuyama, Koji Katayama
  • Publication number: 20070128359
    Abstract: There are disclosed a production apparatus for producing a gallium nitride film semiconductor by HVPE process, a cleaning apparatus for cleaning exhaust gas coming from the above apparatus and an overall production plant for producing a gallium nitride film semiconductor by HVPE process. Therein exhaust piping for exhaust gas in the production apparatus, introduction piping for the cleaning apparatus and exhaust gas piping which connects the production apparatus and the cleaning apparatus are each composed of an electroconductive corrosion-resistant material and are each electrically grounded, thereby surely preventing electrostatic charging due to friction between ammonium chloride powders in the exhaust gas and inside walls of exhaust gas piping, and markedly enhancing operational safety.
    Type: Application
    Filed: February 13, 2007
    Publication date: June 7, 2007
    Applicants: Japan Pionics Co., Ltd, Sumitomo Electric Industires, Ltd.
    Inventors: Kenji OTSUKA, Naoki Muranaga, Kikurou Takemoto
  • Publication number: 20040165871
    Abstract: Affords for semiconductor manufacturing devices a wafer holder and a semiconductor manufacturing device in which it is installed, where in the wafer holder, which has a wafer-carrying side, the isothermal quality of its wafer-carrying side is enhanced. A shaft that supports the wafer holder having a wafer-carrying side is joined to the wafer holder, wherein by making a distance a between the center axis of the shaft and the axial center of the wafer-carrying side 5% or less of the diameter L of the wafer-carrying side, the temperature distribution in the surface of a wafer set into place on the holder can be brought to within ±1.0%. Moreover, making the distance a 1% or less of the diameter L enables the temperature distribution to be brought to within ±0.5%.
    Type: Application
    Filed: February 18, 2004
    Publication date: August 26, 2004
    Applicant: SUMITOMO ELECTRIC INDUSTIRES, LTD.
    Inventors: Masuhiro Natsuhara, Hirohiko Nakata, Manabu Hashikura
  • Publication number: 20040000692
    Abstract: Backgate-characteristics determination method and device that make for curtailing the fabrication of semiconductor circuit elements having defective backgate-characteristics. Initially a first C-V curve 30 representing the relation between a voltage applied to the obverse face of a wafer 20 serving as a substrate for semiconductor circuit elements, and its capacitance, is found. Next, a second C-V curve 32 is found through applying a voltage to the reverse face of the wafer 20. The backgate characteristics for the semiconductor circuit elements are determined based on a voltage-shift amount 34 for the wafer 20, found from the first C-V curve 30 and the second C-V curve 32.
    Type: Application
    Filed: May 1, 2003
    Publication date: January 1, 2004
    Applicant: SUMITOMO ELECTRIC INDUSTIRES, LTD.
    Inventors: Masashi Yamashita, Mitsutaka Tsubokura, Makoto Kiyama