Patents Assigned to Sumitomo Electric
-
Publication number: 20230068932Abstract: A semiconductor device includes a substrate, a channel layer provided on the substrate, a semiconductor layer provided on the channel layer, gate fingers and a gate connection wiring provided on the semiconductor layer, and an insulating film provided between the semiconductor layer and the gate fingers, wherein the gate fingers includes a first gate finger, and a second gate finger closer to the center of the gate fingers in an arrangement direction than the first gate finger, wherein a first distance between a lower surface of the first gate finger in contact with the insulating film and an upper surface of the channel layer in contact with the semiconductor layer is greater than a second distance between a lower surface of the second gate finger in contact with the insulating film and the upper surface of the channel layer in contact with the semiconductor layer.Type: ApplicationFiled: June 17, 2022Publication date: March 2, 2023Applicant: Sumitomo Electric Industries, Ltd.Inventors: Kenya NISHIGUCHI, Akihiro HAYASAKA
-
Publication number: 20230064164Abstract: A cutting tool includes: a cutting section having a cutting edge; a sensor provided in the cutting section; and a communication unit provided in the cutting section. The communication unit transmits, to a processing device provided outside the cutting tool, measurement information relating to measurement results of the sensor and including serial numbers corresponding to the measurement results after a timing of a start of cutting by the cutting edge.Type: ApplicationFiled: January 28, 2021Publication date: March 2, 2023Applicant: Sumitomo Electric Industries, Ltd.Inventor: Hiromitsu KURIYAMA
-
Publication number: 20230060877Abstract: A semiconductor optical device includes a substrate having an optical waveguide, a gain section formed of a compound semiconductor having an optical gain and bonded to an upper surface of the substrate, the gain section having a first mesa, and a first wiring line electrically connected to the gain section. The first mesa of the gain section is optically coupled to the optical waveguide. The substrate includes a first layer, a second layer, and a third layer. The first layer has a higher thermal conductivity than the second layer. The second layer is stacked on the first layer. The third layer is stacked on the second layer. A recess provided in the substrate extends through the third layer to the second layer in the thickness direction. The first wiring line extends from the first mesa of the gain section to the recess.Type: ApplicationFiled: August 29, 2022Publication date: March 2, 2023Applicant: Sumitomo Electric Industries, Ltd.Inventors: Naoko KONISHI, Takehiko KIKUCHI, Hideki YAGI, Nobuhiko NISHIYAMA
-
Patent number: 11591681Abstract: An iron-based sintered body includes a metal matrix and complex oxide particles contained in the metal matrix. When a main viewing field having an area of 176 ?m×226 ?m is taken on a cross section of the iron-based sintered body and divided into a 5×5 array of 25 viewing fields each having an area of 35.2 ?m×45.2 ?m, the complex oxide particles have an average equivalent circle diameter of from 0.3 ?m to 2.5 ?m inclusive, and a value obtained by dividing the total area of the 25 viewing fields by the total number of complex oxide particles present in the 25 viewing fields is from 10 ?m2/particle to 1,000 ?m2/particle inclusive. The number of viewing fields in which no complex oxide particle is present is 4 or less out of the 25 viewing fields.Type: GrantFiled: August 30, 2016Date of Patent: February 28, 2023Assignees: Sumitomo Electric Industries, Ltd., Sumitomo Electric Sintered Alloy, Ltd.Inventors: Tomoyuki Ueno, Koji Yamada, Kazuya Takizawa, Yuki Adachi, Tetsuya Hayashi
-
Patent number: 11591695Abstract: A surface coated member having improved stability and a longer service life is provided. The surface coated member includes a base member and a hard coating formed on a surface thereof. The hard coating is constituted of one or more layers. At least one layer among the layers is a layer including hard particles. The hard particles include a multilayer structure having a first unit layer and a second unit layer being layered alternately. The first unit layer includes a first compound. The second unit layer includes a second compound. The first compound and the second compound are respectively made of one or more kind of element selected from the group consisting of a group 4 element, a group 5 element, a group 6 element of a periodic table, and Al, and one or more kind of element selected from the group consisting of B, C, N, and O.Type: GrantFiled: October 9, 2019Date of Patent: February 28, 2023Assignee: Sumitomo Electric Hardmetal Corp.Inventors: Anongsack Paseuth, Kazuo Yamagata, Susumu Okuno, Hideaki Kanaoka, Hiroyuki Morimoto, Minoru Itoh
-
Patent number: 11591266Abstract: A cubic boron nitride sintered material includes: more than or equal to 50 volume % and less than 80 volume % of cubic boron nitride grains; and more than 20 volume % and less than or equal to 50 volume % of a binder phase, and when an oxygen content is measured in a direction perpendicular to an interface between cubic boron nitride grains using TEM-EDX, a first region having an oxygen content larger than an average value of an oxygen content of a cubic boron nitride grain exists, the interface exists in the first region, and a length of the first region along the direction perpendicular to the interface is more than or equal to 0.1 nm and less than or equal to 10 nm.Type: GrantFiled: July 17, 2020Date of Patent: February 28, 2023Assignees: Sumitomo Electric Industries, Ltd., SUMITOMO ELECTRIC HARDMETAL CORP.Inventors: Hisaya Hama, Katsumi Okamura, Akito Ishii, Satoru Kukino
-
Patent number: 11595002Abstract: This method for detecting a poor module-mounting-state in a concentrator photovoltaic apparatus includes: photographing a surface of an array by an imaging device; obtaining an image in which a virtual image, magnified through a condenser lens, of a light receiving portion including a cell and a vicinity thereof is formed, and a collection of pixels of the virtual image forms a composite virtual image of an entirety of the light receiving portion, the composite virtual image being projected over a plurality of modules; and detecting a poor module-mounting-state based on a form of the composite virtual image.Type: GrantFiled: December 12, 2018Date of Patent: February 28, 2023Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Takashi Iwasaki, Koji Mori, Kenji Saito, Kazushi Iyatani, Yoshikazu Kogetsu
-
Patent number: 11595010Abstract: An optical receiver disclosed includes a bias terminal, an input terminal, a photodiode, an amplifier circuit, a first resistor, a bypass circuit, a filter circuit, and a control circuit. The photodiode receives a bias from the filter circuit through the bias terminal, and outputs a current signal to the amplifier circuit through the input terminal. The amplifier circuit converts an input current to an output voltage. The bypass circuit electrically connected to the input terminal decreases a first input impedance viewed from the input terminal, when activated, and increases the first input impedance, when deactivated. The filter circuit increases a second input impedance viewed from the bias terminal, when a dumping function thereof is activated, and decreases the second input impedance, when the dumping function is deactivated. The control circuit activates the dumping function and the bypass circuit, when the output voltage is larger than a certain voltage.Type: GrantFiled: October 14, 2020Date of Patent: February 28, 2023Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Naoki Itabashi, Keiji Tanaka
-
Patent number: 11594359Abstract: A reactor that includes a coil having a wound portion; a magnetic core; a holding member provided at both ends of the wound portion; a mold resin by which the coil and the holding member are integrated into one piece; a casing that houses an assembly that includes the coil, the magnetic core, and the holding member; and a potting resin that fills up the casing to seal at least a part of the assembly.Type: GrantFiled: May 21, 2020Date of Patent: February 28, 2023Assignees: AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO WIRING SYSTEMS, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Takashi Misaki, Shinichiro Yamamoto
-
Patent number: 11594507Abstract: A method for manufacturing a semiconductor device includes forming a thermosetting resin film on a first metal layer, forming an opening in the resin film, forming a second metal layer that covers a region from an upper surface of the first metal layer exposed from the opening of the resin film to an upper surface of the resin film, performing heat treatment at a temperature equal to or higher than a temperature at which the resin film is cured after forming the second metal layer, forming a cover film that covers the upper surface of the resin film and a side surface of the second metal layer after performing the heat treatment, and forming a solder on an upper surface of the second metal layer exposed from an opening of the cover film after forming the cover film.Type: GrantFiled: April 22, 2021Date of Patent: February 28, 2023Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventor: Keita Matsuda
-
Patent number: 11594346Abstract: An aluminum alloy contains equal to or more than 0.005 mass % and equal to or less than 2.2 mass % of Fe, and a remainder of Al and an inevitable impurity. In a transverse section of the aluminum alloy wire, a surface-layer void measurement region in a shape of a rectangle having a short side length of 30 ?m and a long side length of 50 ?m is defined within a surface layer region extending from a surface of the aluminum alloy wire by 30 ?m in a depth direction, and a total cross-sectional area of voids in the surface-layer void measurement region is equal to or less than 2 ?m2.Type: GrantFiled: April 25, 2022Date of Patent: February 28, 2023Assignees: Sumitomo Electric Industries, Ltd., AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd.Inventors: Misato Kusakari, Tetsuya Kuwabara, Yoshihiro Nakai, Taichiro Nishikawa, Yasuyuki Otsuka, Hayato Ooi
-
Patent number: 11591252Abstract: A production method and others according to the present embodiment are provided with a structure for effectively preventing occurrence of accidental spiking during drawing of a preform. In order to control the residual He-concentration in the center part of the preform, a transparent glass rod that has a predetermined outer diameter and is already sintered but is not doped with an alkali metal yet is annealed in in the atmosphere not containing He gas for an annealing time determined by referring to result data in which the relationship between the annealing time and the residual He-concentration is previously recorded for each outer diameter. In the result data, actually measured data of the residual He-concentration in a produced optical fiber preform and the annealing time are accumulated as annealing treatment results.Type: GrantFiled: April 13, 2018Date of Patent: February 28, 2023Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Takumi Yonemura, Noboru Yamazaki, Satoshi Tanaka
-
Publication number: 20230054503Abstract: A tool main body to which an insert is attachable, in which the tool main body is made of sintered metal material, and the sintered metal material includes a parent phase made of a metal and a plurality of pores present in the parent phase.Type: ApplicationFiled: October 29, 2020Publication date: February 23, 2023Applicants: Sumitomo Electric Industries, Ltd., Sumitomo Electric Sintered Alloy, Ltd.Inventors: Tomoyuki ISHIMINE, Mitsuhiro GOTO, Shigeki EGASHIRA, Kazunari SHIMAUCHI
-
Publication number: 20230057015Abstract: The light modulator includes a substrate having a main surface including a first area, a second area, and a third area, a first III-V compound semiconductor layer of a first conductivity-type provided on the first area, a second III-V compound semiconductor layer of a first conductivity-type or a second conductivity-type provided on the second area, a core provided on the third area and including a group III-V compound semiconductor, and an electrode connected to the first III-V compound semiconductor layer. The first III-V compound semiconductor layer includes a first portion having a thickness smaller than a thickness of the core in a second direction orthogonal to the main surface and a second portion having a thickness larger than the thickness of the first portion in the second direction. The second portion is disposed between the first portion and the core.Type: ApplicationFiled: August 12, 2022Publication date: February 23, 2023Applicant: Sumitomo Electric Industries, Ltd.Inventors: Naoya KONO, Hajime TANAKA, Naoki FUJIWARA
-
Publication number: 20230056385Abstract: A differential signal transmission cable includes an insulation layer extending in a longitudinal direction of the differential signal transmission cable, a pair of signal lines extending in the longitudinal direction and buried inside the insulation layer, an intermediate layer covering an outer circumferential surface of the insulation layer, a shield, and catalyst particles. The shield includes an electroless plating layer covering an outer circumferential surface of the intermediate layer. The catalyst particles are dispersed between the intermediate layer and the electroless plating layer.Type: ApplicationFiled: January 30, 2020Publication date: February 23, 2023Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Kengo GOTO, Akihisa HOSOE, Yuto KOBAYASHI, Yuji OCHI
-
Publication number: 20230054259Abstract: A semiconductor device includes a substrate, a semiconductor stacking portion formed on the substrate, a silicon nitride passivation film covering the surface of the semiconductor stacking portion, and oxygen atoms existing at an interface between the silicon nitride passivation film and the semiconductor stacking portion. The semiconductor stacking portion includes a plurality of nitride semiconductor layers. The interfacial oxygen content at the passivation film and stacking portion interface is 0.6×1015 oxygen atoms/cm2 or less.Type: ApplicationFiled: October 4, 2022Publication date: February 23, 2023Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Kazuhide SUMIYOSHI, Masaya OKADA, Kazutaka INOUE, Takumi YONEMURA
-
Patent number: 11589455Abstract: The electronic module including a metal base, a ceramic substrate, and a die-capacitor is disclosed. The ceramic substrate is mounted on the metal base via eutectic solder. The ceramic substrate includes a main substrate having a back surface facing the metal base and a front surface opposite to the back surface, and a back metal layer placed on the back surface of the main substrate and joined to the eutectic solder. The die-capacitor is mounted on the front surface of the ceramic substrate along one edge of the ceramic substrate. The back surface of the ceramic substrate is provided with an exposure region where the back metal layer is not provided. The exposure region includes a main region corresponding to an outer shape of the die-capacitor spreading along the front surface and an edge region extending from the main region to the one edge of the ceramic substrate.Type: GrantFiled: July 17, 2019Date of Patent: February 21, 2023Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventors: Akitada Kodama, Masato Furukawa
-
Patent number: 11588476Abstract: An amplitude modulation circuit includes: first, second, and third input terminals; first and second output terminals; a current source; first and second transistors including a base electrically connected to the first and second input terminals, a collector electrically connected to the first and second output terminals, and an emitter electrically connected to a grounding terminal via the current source; first and second resistive elements electrically connected between the first and second output terminals and a power line; and a first MOS transistor including a drain connected to the first output terminal, a source connected to the second output terminal, and a gate connected to the third input terminal. The MOS transistor is configured to operate in a non-saturated region, and a resistance between the source and the drain of the MOS transistor is larger than resistances of the first and second resistive elements.Type: GrantFiled: November 9, 2021Date of Patent: February 21, 2023Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Hiroshi Uemura, Keiji Tanaka
-
Patent number: 11588441Abstract: A semiconductor amplifier 1 includes transistors 21a and 21b mounted side by side on a bottom plate 2 in a space in a package 6, a matching circuit 22a mounted between the transistors 21a, 21b on the bottom plate 2, a matching circuit 22b mounted on an opposite side of the transistor 21b from the transistor 21a on the bottom plate 2, an input terminal TIN installed on one side of a wiring substrate 3, an output terminal TOUT installed on the other side of the wiring substrate 3, and gate bias terminals T1G and T2G and drain bias terminals T1D and T2D installed at positions with the input terminal TIN and the output terminal TOUT of the wiring substrate 3, and the transistor 21a, the matching circuit 22a, the transistor 21b, and the matching circuit 22b are linearly placed between the input terminal TIN and the output terminal TOUT.Type: GrantFiled: December 17, 2020Date of Patent: February 21, 2023Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventor: Naoyuki Miyazawa
-
Publication number: 20230050674Abstract: A wiring module to be attached to a plurality of power storage devices arranged in an arrangement direction, the wiring module including: an insulating protector; and a flexible printed wiring board disposed in the protector, wherein the protector has a shape extending in the arrangement direction, the flexible printed wiring board includes a main body part extending in the arrangement direction and disposed in the protector, and an extension piece extending from the main body part, the extension piece has a curved portion that is curved, and the extension piece is inverted by the curved portion, and the protector includes a locking part that locks to the extension piece from a direction to prevent the curved portion from deforming back to an original shape thereof.Type: ApplicationFiled: September 4, 2020Publication date: February 16, 2023Applicants: AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO WIRING SYSTEMS, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Hideo TAKAHASHI, Shinichi TAKASE, Hiroki SHIMODA