Patents Assigned to Sumitomo Mitsubishi Silicon Corp.
  • Patent number: 7947572
    Abstract: A semiconductor structure and a method of manufacturing a silicon on insulator (SOI) structure having a silicon germanium (SiGe) layer interposed between the silicon and the insulator. According to one manufacturing method, a first SiGe layer, a silicon layer, and a second SiGe layer are epitaxially grown in sequence over a first substrate, and then an insulating layer is formed on the second SiGe layer. Then, impurity ions are implanted into a predetermined location of the first substrate underlying the first SiGe layer to form an impurity implantation region. A second substrate is bonded to the insulating layer on the first substrate. After the first substrate is separated along the impurity implantation region and removed, the first SiGe layer remaining on the surface of the separated region is removed so that the surface of the silicon layer may be exposed.
    Type: Grant
    Filed: April 13, 2010
    Date of Patent: May 24, 2011
    Assignees: Sumitomo Mitsubishi Silicon Corp., Jeagun Park
    Inventors: Jeagun Park, Kenji Tomizawa, Gonsub Lee, Eiji Kamiyama
  • Patent number: 7741193
    Abstract: A semiconductor structure and a method of manufacturing a silicon on insulator (SOI) structure having a silicon germanium (SiGe) layer interposed between the silicon and the insulator. According to one manufacturing method, a first SiGe layer, a silicon layer, and a second SiGe layer are epitaxially grown in sequence over a first substrate, and then an insulating layer is formed on the second SiGe layer. Then, impurity ions are implanted into a predetermined location of the first substrate underlying the first SiGe layer to form an impurity implantation region. A second substrate is bonded to the insulating layer on the first substrate. After the first substrate is separated along the impurity implantation region and removed, the first SiGe layer remaining on the surface of the separated region is removed so that the surface of the silicon layer may be exposed.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: June 22, 2010
    Assignees: Sumitomo Mitsubishi Silicon Corp., Jeagun Park
    Inventors: Jeagun Park, Kenji Tomizawa, Gonsub Lee, Eiji Kamiyama
  • Patent number: 7180138
    Abstract: A semiconductor structure and a method of manufacturing a silicon on insulator (SOI) structure having a silicon germanium (SiGe) layer interposed between the silicon and the insulator. According to one manufacturing method, a first SiGe layer, a silicon layer, and a second SiGe layer are epitaxially grown in sequence over a first substrate, and then an insulating layer is formed on the second SiGe layer. Then, impurity ions are implanted into a predetermined location of the first substrate underlying the first SiGe layer to form an impurity implantation region. A second substrate is bonded to the insulating layer on the first substrate. After the first substrate is separated along the impurity implantation region and removed, the first SiGe layer remaining on the surface of the separated region is removed so that the surface of the silicon layer may be exposed.
    Type: Grant
    Filed: June 13, 2005
    Date of Patent: February 20, 2007
    Assignees: Sumitomo Mitsubishi Silicon Corp., Jeagun Park
    Inventors: Jeagun Park, Kenji Tomizawa, Gonsub Lee, Eiji Kamiyama