Abstract: Embodiments of the present invention include techniques for detecting power sources. In one embodiment, the present invention includes a method of detecting a power source comprising coupling a power source to a portable electronic device, the power source comprising a first supply voltage and a second supply voltage, and at least a first data terminal and a second data terminal, coupling a resistor to the first data terminal a predetermined time period after the power source is coupled to the electronic device, detecting the voltage on the first data terminal and second data terminal, and generating a first signal corresponding to a first power source if the first and second data terminals have the same voltage after said predetermined time period, and generating a second signal corresponding to a second power source if the first and second data terminals have differential voltages after said predetermined time period.

Abstract: Embodiments of the present invention include techniques for charging a battery using a regulator. In one embodiment, the present invention includes an electronic circuit comprising a regulator having an input coupled to a power source for receiving a voltage and a current and an output for providing an output current, an input voltage detection circuit coupled to the power source, and an adjustable current limit circuit for controlling the input or output current of the regulator, wherein input voltage detection circuit monitors the voltage from the power source and the adjustable current limit circuit changes the input or output current of the regulator to optimize the power drawn from power source.

Abstract: Embodiments of the present invention include systems and methods of controlling power in battery operated systems. In one embodiment, the present invention includes a switching regulator for boosting voltage on a depleted battery to power up a system. The system may communicate with an external system to increase the current received from the external system. Embodiments of the present invention include circuits for controlling power received from external power sources such as a USB power source. In another embodiment, input-output control techniques are disclosed for controlling the delivery of power to a system or charging a system battery, or both, from an external power source.

Abstract: A system and method is provided to accomplish distributed power sequencing function of a large electronics system with minimum number of signals in the sequencing network without compromising the flexibility and expandability. In one embodiment of the invention, the power sequencing function is accomplished with two signals of the sequencing network: power_on/power_off signal and SEQ_LINK signal. The power_on/power_off signal controls whether the sequencing is in power_on mode for turning on power to multiple devices in a predetermined sequence or power_off mode for for turning off power to multiple devices in a reverse sequence. The SEQ_LINK signal controls when the sequence counters, located in each participating device, are allowed to count to the subsequent state. Each sequencing logic circuit of these participating devices responds to a predetermined sequence position to enable the power on or power off of the power supply it controls.

Abstract: In one embodiment the present invention includes a system and method of charging a battery using a switching regulator. In one embodiment, a switching regulator receives an input voltage and input current. The output of the switching regulator is coupled to a battery to be charged. The switching regulator provides a current into the battery that is larger than the current into the switching regulator. As the voltage on the battery increases, the current provided by the switching regulator is reduced. The present invention may be implemented using either analog or digital techniques for reducing the current into the battery as the battery voltage increases.

Abstract: Embodiments of the present invention include techniques for charging a battery using a switching regulator. Some embodiments include programmable switching battery chargers that can be configured using digital techniques. Other embodiments include switching battery chargers that modify the battery current based on sensed circuit conditions such as battery voltage or input current to the switching regulator. In one embodiment, the present invention includes a USB battery charger.

Abstract: A feedback control-loop system that employs an active DC output control circuit is disclosed which compares an input parameter measurement against a target specification associated with the input parameter measurement. In one embodiment, the active DC output control circuit receives an input signal for laser bias adjustment. In another embodiment, the active DC output control circuit receives a motor speed input from a source, such as a tachometer, for motor speed adjustment. In another embodiment, the active DC output control circuit receives an input power amplifier measurement for wireless applications.

Abstract: Active back bias voltage, applied to wells of N-MOS and P-MOS transistors of a small geometry integrated circuit, is used to set the threshold voltages and leakage currents precisely in order to improve speed and at the same time control device sub-threshold leakage. The active back bias applies a voltage to the well of devices on the small geometry integrated circuit. The voltage with increases until the leakage current goes to a predetermined level. If the leakage increases with age, temperature, VDD voltage or other conditions the bias supply from the active back bias generator compensates.

Abstract: An integrated circuit with improved testability includes a test logic component that replaces a corresponding regular logic component and that generates a logic high or low whenever a test input is activated. Alternatively, it may generate either high or low depending on which of two test inputs is activated. A test program may be augmented with instructions to activate such test inputs. An integrated circuit design may be analyzed to select a node that is not covered by a test program and to identify which logic component generates an output on the node. Then the design may be altered to replace the identified logic component with a corresponding test logic component. Test coverage analysis may be based on determining whether the test program toggles the node, or determining whether a stuck at fault on the node propagates so as to be observed.

Abstract: A programmable and non-volatile analog signal storage structure and method are disclosed that employ two non-volatile cells which are arranged as a differential transistor pair. The non-volatile transistor at the positive (or non-inverting) terminal of the amplifier is referred to as the reference cell, while the non-volatile transistor on the negative (or inverting) input of the amplifier is referred to as the storage cell. The structure comprises a storage cell and a reference cell that produces a voltage which is independent of temperature and supply voltage variation. Additionally, the circuit structure is capable of operating at low supply voltage levels (<1.5V).

Abstract: Digital-to-analog converter architecture guarantees monotonicity and partial compensation for integral non-linearity. Two stages are separated by a unity-gain operational amplifier, wherein the first stage is a 1-bit resistor string-converter, having one end at reference high voltage, and the other end at reference low voltage, and the second stage is a multi-bit resistor string converter. The architecture relieves matching accuracy necessary for 1-bit front end. Resistor mismatch is compensated by varying buffer amplifier offset-voltage, and ensuring amplifier output is halfway between reference voltages; this improves integral non-linearity, or absolute accuracy, by the amount of mismatch present in the resistor string. Buffer amplifier at output of second stage of DAC controls INL error by varying offset voltage.

Abstract: The invention includes a segmented digital-to-analog converter (DAC) processing an N-bit input digital signal. A first segment converter processes the most significant bits and subsequent segment converters process the least significant bits of the N-bit input digital signal. The first segment converter includes ballast resistors that nullify the effect of any imbalance of the resistance of the first segment DAC versus the sum of the resistances in the remaining segment DACs. The first segment may be a 2, 4, 6, 8 or higher bit DAC while the second or subsequent segments may similarly be 2, 4, 6, 8, or higher bit DACs.

Abstract: The invention provides a single input pin on an integrated circuit chip that serves multiple functions during normal, test, and program modes. A first voltage detector detects a first predetermined high voltage level to place an integrated circuit in test mode. A second voltage detector detects a second predetermined high voltage level to place the integrated circuit in program mode. A high level switch is triggered to activate a pulse shaping circuit, which ramps up voltage gradually to prevent causing damage to programmable cells.

Abstract: Analog integrated circuits have their individual characteristics compensated by the settings of self-contained non-volatile memory elements. The settings of the memory elements are determined by repeatedly testing the possible values until an optimal one is chosen. The testing process is accelerated by eliminating the need to re-write the non-volatile memory for each value that is tested.

Abstract: A method and apparatus for tracking and controlling one or more voltage and current supplies during a transition between and off-state to an on-state, or from an on state to an off-state, is enabled by detecting a voltage or current transition and controlling the voltage or current supply transition within a specified upper and lower limit about a reference transition.

Abstract: A configurable integrated circuit and method for trimming a desirable combination of analog and digital functions and customizing pin assignments by programming nonvolatile memory. Functional enhancement and chip compatibility are achieved by configuring an integrated circuit with specified analog and digital settings for operation with an external chip. Multiple NV registers with designated bits that correspond to activating, deactivating, trimming, or changing analog functions including internal voltages, bandgap, and oscillating frequencies.

Abstract: A phased-lock loop is disclosed for capturing the frequency of the input signal by adjusting a tunable oscillator such that a zero-crossing detector detects a zero-crossing point of the input signal relative to a predetermined number of counts at a counter where a control logic increments a tuning counter to increase the frequency at the tunable oscillator while decrements the tuning counter to decrease the frequency in the tunable oscillator. The predetermined number of counts at the counter representing one period, a fraction of a period, or a multiple of a period of the frequency of the input signal. The control logic adjusts the count at the tuning counter until the tunable oscillator generates an internal frequency that captures the frequency of the input signal.

Abstract: A battery type identification system for determining the type of a selected battery and its operational status as a function of type. A battery has spaced bands of selected conductivity to define an identification code used to identify the battery. An appliance using batteries (e.g., a consumer product) includes an array of conductivity detectors spaced to engage corresponding battery identification bands. The battery types identification system determines battery kinds of predetermined type and then determines the voltage of the battery to assess its operability status.