Abstract: Embodiments of the present invention include electronic circuits, systems, and methods for charging a battery. In one embodiment, the present invention includes a method, which may be implemented by an integrated circuit, comprising charging the battery using a constant current until the voltage on the battery increases to a first voltage level, and charging the battery using a constant voltage, wherein the constant voltage is set to a second voltage level. The constant current charging transitions to constant voltage charging when the voltage on the battery reaches the first voltage level, where the first voltage level is greater than the second voltage level.

Abstract: Embodiments of the present invention include techniques for sensing current. In one embodiment, a switch in a switching regulator is coupled to a power supply. Input current from the supply is translated into an output current of the switching regulator. A signal corresponding to the output current is generated. The signal is selectively turned off with the input switch is open. Accordingly, the signal tracks the input current into the regulator. The signal may be used to determine the input current. In one embodiment, the signal is a voltage signal generated by a current corresponding to the output current provided into a resistor.

Abstract: Embodiments of the present invention include an electronic circuit for performing current sensing. In one embodiment, the present invention includes a first switching transistor and a second switching transistor both coupled to receive a first switching current and a switching signal, and one or more transistors coupled in a first series. A first terminal of an initial transistor in the first series is coupled to a second terminal of the second switching transistor. A second terminal of a last transistor in the first series is coupled to a reference voltage. The first switching current is coupled to a second node between the second terminal of the second switching transistor and the first terminal of the initial transistor in the first series. In this manner, the circuit produces a switching voltage corresponding to said first switching current.

Abstract: In one embodiment the present invention includes a method of controlling a switching regulator based on a derived input current. In one embodiment, an output current of said switching regulator is detected and used to generate a first voltage or current signal corresponding to the output current. Additionally, a switching signal of said switching regulator is detected and used to generate a second voltage or current signal corresponding to the switching signal. The resulting signals may be combined to produce a voltage or current signal corresponding to an input current of said switching regulator. The switching signal may be modified based on the derived voltage or current signal and used to control the system.

Abstract: Embodiments of the present invention include techniques for charging a battery. In one embodiment, the present invention includes a method comprising determining if a maximum current output of a power source is above a threshold, configuring a regulator coupled to the power source, wherein the regulator is configured in a pass mode if the maximum current output is above the threshold, and wherein the regulator is configured in a regulation mode if the maximum current output is below the threshold, and generating pulses to a battery, wherein an output of the regulator is coupled to the battery when a pulse is being generated, and the output of the regulator is decoupled from the battery when a pulse is not being generated. In other embodiments, the techniques may be embodied in a circuit including a detection circuit and a switching regulator coupled to a battery through a pulse circuit.

Abstract: In one embodiment the present invention includes a method of charging a battery comprising storing a plurality of charging parameters in one or more programmable data storage elements. The charging parameters may be used to program a variety of battery charging parameters including constant currents, voltages, thresholds, timers, or temperature controls. In one embodiment, the present invention includes a software algorithm that changes the charging parameters to improve battery charging efficiency.

Abstract: A system and method is provided to accomplish distributed power sequencing function of a large electronics system with minimum number of signals in the sequencing network without compromising the flexibility and expandability. In one embodiment of the invention, the power sequencing function is accomplished with two signals of the sequencing network: power_on/power_off signal and SEQ_LINK signal. The power_on/power_off signal controls whether the sequencing is in power_on mode for turning on power to multiple devices in a predetermined sequence or power_off mode for for turning off power to multiple devices in a reverse sequence. The SEQ_LINK signal controls when the sequence counters, located in each participating device, are allowed to count to the subsequent state. Each sequencing logic circuit of these participating devices responds to a predetermined sequence position to enable the power on or power off of the power supply it controls.

Abstract: Embodiments of the present invention include techniques for detecting power sources. In one embodiment, the present invention includes a method of detecting a power source comprising coupling a power source to a portable electronic device, the power source comprising a first supply voltage and a second supply voltage, and at least a first data terminal and a second data terminal, coupling a resistor to the first data terminal a predetermined time period after the power source is coupled to the electronic device, detecting the voltage on the first data terminal and second data terminal, and generating a first signal corresponding to a first power source if the first and second data terminals have the same voltage after said predetermined time period, and generating a second signal corresponding to a second power source if the first and second data terminals have differential voltages after said predetermined time period.

Abstract: Embodiments of the present invention include techniques for charging a battery using a regulator. In one embodiment, the present invention includes an electronic circuit comprising a regulator having an input coupled to a power source for receiving a voltage and a current and an output for providing an output current, an input voltage detection circuit coupled to the power source, and an adjustable current limit circuit for controlling the input or output current of the regulator, wherein input voltage detection circuit monitors the voltage from the power source and the adjustable current limit circuit changes the input or output current of the regulator to optimize the power drawn from power source.

Abstract: Embodiments of the present invention include systems and methods of controlling power in battery operated systems. In one embodiment, the present invention includes a switching regulator for boosting voltage on a depleted battery to power up a system. The system may communicate with an external system to increase the current received from the external system. Embodiments of the present invention include circuits for controlling power received from external power sources such as a USB power source. In another embodiment, input-output control techniques are disclosed for controlling the delivery of power to a system or charging a system battery, or both, from an external power source.

Abstract: A system and method is provided to accomplish distributed power sequencing function of a large electronics system with minimum number of signals in the sequencing network without compromising the flexibility and expandability. In one embodiment of the invention, the power sequencing function is accomplished with two signals of the sequencing network: power_on/power_off signal and SEQ_LINK signal. The power_on/power_off signal controls whether the sequencing is in power_on mode for turning on power to multiple devices in a predetermined sequence or power_off mode for for turning off power to multiple devices in a reverse sequence. The SEQ_LINK signal controls when the sequence counters, located in each participating device, are allowed to count to the subsequent state. Each sequencing logic circuit of these participating devices responds to a predetermined sequence position to enable the power on or power off of the power supply it controls.

Abstract: Embodiments of the present invention include techniques for charging a battery using a switching regulator. Some embodiments include programmable switching battery chargers that can be configured using digital techniques. Other embodiments include switching battery chargers that modify the battery current based on sensed circuit conditions such as battery voltage or input current to the switching regulator. In one embodiment, the present invention includes a USB battery charger.

Abstract: In one embodiment the present invention includes a system and method of charging a battery using a switching regulator. In one embodiment, a switching regulator receives an input voltage and input current. The output of the switching regulator is coupled to a battery to be charged. The switching regulator provides a current into the battery that is larger than the current into the switching regulator. As the voltage on the battery increases, the current provided by the switching regulator is reduced. The present invention may be implemented using either analog or digital techniques for reducing the current into the battery as the battery voltage increases.

Abstract: A feedback control-loop system that employs an active DC output control circuit is disclosed which compares an input parameter measurement against a target specification associated with the input parameter measurement. In one embodiment, the active DC output control circuit receives an input signal for laser bias adjustment. In another embodiment, the active DC output control circuit receives a motor speed input from a source, such as a tachometer, for motor speed adjustment. In another embodiment, the active DC output control circuit receives an input power amplifier measurement for wireless applications.

Abstract: Active back bias voltage, applied to wells of N-MOS and P-MOS transistors of a small geometry integrated circuit, is used to set the threshold voltages and leakage currents precisely in order to improve speed and at the same time control device sub-threshold leakage. The active back bias applies a voltage to the well of devices on the small geometry integrated circuit. The voltage with increases until the leakage current goes to a predetermined level. If the leakage increases with age, temperature, VDD voltage or other conditions the bias supply from the active back bias generator compensates.

Abstract: An integrated circuit with improved testability includes a test logic component that replaces a corresponding regular logic component and that generates a logic high or low whenever a test input is activated. Alternatively, it may generate either high or low depending on which of two test inputs is activated. A test program may be augmented with instructions to activate such test inputs. An integrated circuit design may be analyzed to select a node that is not covered by a test program and to identify which logic component generates an output on the node. Then the design may be altered to replace the identified logic component with a corresponding test logic component. Test coverage analysis may be based on determining whether the test program toggles the node, or determining whether a stuck at fault on the node propagates so as to be observed.

Abstract: A programmable and non-volatile analog signal storage structure and method are disclosed that employ two non-volatile cells which are arranged as a differential transistor pair. The non-volatile transistor at the positive (or non-inverting) terminal of the amplifier is referred to as the reference cell, while the non-volatile transistor on the negative (or inverting) input of the amplifier is referred to as the storage cell. The structure comprises a storage cell and a reference cell that produces a voltage which is independent of temperature and supply voltage variation. Additionally, the circuit structure is capable of operating at low supply voltage levels (<1.5V).

Abstract: Digital-to-analog converter architecture guarantees monotonicity and partial compensation for integral non-linearity. Two stages are separated by a unity-gain operational amplifier, wherein the first stage is a 1-bit resistor string-converter, having one end at reference high voltage, and the other end at reference low voltage, and the second stage is a multi-bit resistor string converter. The architecture relieves matching accuracy necessary for 1-bit front end. Resistor mismatch is compensated by varying buffer amplifier offset-voltage, and ensuring amplifier output is halfway between reference voltages; this improves integral non-linearity, or absolute accuracy, by the amount of mismatch present in the resistor string. Buffer amplifier at output of second stage of DAC controls INL error by varying offset voltage.

Abstract: The invention includes a segmented digital-to-analog converter (DAC) processing an N-bit input digital signal. A first segment converter processes the most significant bits and subsequent segment converters process the least significant bits of the N-bit input digital signal. The first segment converter includes ballast resistors that nullify the effect of any imbalance of the resistance of the first segment DAC versus the sum of the resistances in the remaining segment DACs. The first segment may be a 2, 4, 6, 8 or higher bit DAC while the second or subsequent segments may similarly be 2, 4, 6, 8, or higher bit DACs.

Abstract: The invention includes a segmented digital-to-analog converter (DAC) processing an N-bit input digital signal. A first segment converter processes the most significant bits and subsequent segment converters process the least significant bits of the N-bit input digital signal. The first segment converter includes ballast resistors that nullify the effect of any imbalance of the resistance of the first segment DAC versus the sum of the resistances in the remaining segment DACs. The first segment may be a 2, 4, 6, 8 or higher bit DAC while the second or subsequent segments may similarly be 2, 4, 6, 8, or higher bit DACs.