Abstract: Custom application development environment modules may be designed to work with a first application development environment. This functionality may be extended to a second application development environment by first creating user interface elements for the second application development environment. User interface elements from the custom application development environment modules may be separated, forming user interface elements for the first application development environment. New general elements may then be created, which are compatible with both the first application development environment and the second application development environment. The general elements may be combined with non-user interface elements from the custom application development environment modules to arrive at a series of generalized classes.

Abstract: A method for debugging a computer program, includes (a) selecting a section of the computer program assembled in a machine-language, the computer program using a set of registers, the section including a plurality of machine-language instructions, (b) disassembling the plurality of machine-language instructions into mnemonic instructions, (c) automatically determining and selecting registers used by the mnemonic instructions corresponding to the section from among the set of registers, and (d) displaying the selected registers to a user. The method may further include displaying the mnemonic instructions, indicating a specific mnemonic instruction, and displaying a value of each of the selected registers before the execution of the indicated mnemonic instruction. The method may further include providing an option to a user to manually select registers to be displayed.

Abstract: The present invention utilizes peer groups in a distributed architecture to decentralize its task dispatching and post-processing functions and to provide the ability to manage and run many different applications simultaneously, in an efficient and reliable manner. Jobs may be submitted to a task dispatcher or to a monitor which distributes the jobs to task dispatchers. Through a series of processes, the task dispatchers may then distribute the jobs to workers. This allows work to be distributed without utilizing a centralized server.

Abstract: The present invention utilizes peer groups in a distributed architecture to decentralize its task dispatching and post-processing functions and to provide the ability to manage and run many different applications simultaneously, in an efficient and reliable manner. Jobs may be submitted to a task dispatcher or to a monitor which distributes the jobs to task dispatchers. Through a series of processes, the task dispatchers may then distribute the jobs to workers. This allows work to be distributed without utilizing a centralized server.

Abstract: The monitoring of the performance of computer code may be accomplished by inserting starting and ending hooks in the computer code, the hooks indicating the start or end of a group, feature, or subfeature. These hooks may gather the time at which they are executed, and these values may be appended to an extensible markup language file. This file may then be utilized to gauge the performance of various portions of the computer code.

Abstract: An existing neutral operating system (OS) signal is utilized to notify a virtual machine (VM) about a change to its execution parameters. The signal is predefined to indicate that an execution parameter should be changed, and upon receipt, the VM may look up a file in a predefined location, the file containing the new command line parameters. The VM may then modify its parameters to match the file, and continue with its execution, thus providing a mechanism for altering VM execution parameters at runtime.

Abstract: A testbench for an integrated circuit (IC) design including a chain of scan circuits having a memory characteristic is verified by: (a) dividing the chain of scan circuits and creating a plurality of partitions, each partition including at least one logic cone output, each scan circuit belonging to one of the partition as a logic cone output; (b) generating a partitioned netlist for each partition from a full netlist for the IC design, the partitioned netlist including at least one logic cone, the logic cone extending from the logic cone output to at least one logic cone input; (c) generating a partitioned testbench for each partition from the full testbench based on the partitioned netlists; and (d) performing verification for the testbench by simulating the partitioned testbenches on the corresponding partitioned netlists.

Abstract: A method allocates computing resources from a resource pool. Each job request includes attributes and a unique identifier. A digital signature is generated for each job request based on the combination of the attributes. The identifier is associated with the digital signature. Job requests having identical attributes are grouped together.

Abstract: A solution is provided to reshape irregularly-shaped computer graphics images in order to reduce the number of rectangles generated for transmission. It may be used any time it is useful to compress a set of digital image data from an irregularly-shaped region of pixels. A post-shaping process may be utilized wherein rectangles in a destination window are examined and any touching (or possibly nearby) rectangles are merged into a single rectangle. Alternatively, a pre-shaping process may be utilized wherein images drawn with a single command are merged into a single rectangle. Each of these processes has advantages and disadvantages which may make one or the other preferable, depending upon the circumstances. Additionally, both processes may be used together if desired.

Abstract: Repeating image content in a graphics image may be detected by identifying certain commands, known generally as “tile commands”. If a tile command is detected, the fact that a portion of an image was created with a tile command may be stored along with the portion of the image. This allows for well-informed decision making when transmission of the image is to be performed. For example, this allows for the transmission of a single tile, and subsequent transmission of local copy commands to repeat the single tile. This can be very useful in speeding transmission of background images or other repeating images.

Abstract: The storing of not only image content but information regarding what commands were used to create the image allows for well-informed decision making. The drawing commands are recorded and may be stored in a data structure. This data structure may then be accessed at the time of compression, and the selection of which compression technique to use may be based on the drawing commands. Pixmaps are data structures holding pixel values corresponding to an image in memory. The data structure utilized here may be a linked list identifying fill regions. This permits the well-informed decision making to be accomplished even when pixmaps are copied to realized (on-screen) windows or other pixmaps.

Abstract: The storing of not only image content but information regarding what commands were used to create the image allows for well-informed decision making. The drawing commands are recorded and may be stored in a data structure. This data structure may then be accessed at the time of compression, and the selection of which compression technique to use may be based on the drawing commands. Thus, certain codecs may be applied to certain portions of the image, resulting in a more efficiently compressed image. Pixmaps are data structures holding pixel values corresponding to an image in memory. The data structure utilized here may be a separate RGB pixmap region associated with a pixmap holding image data. This permits the well-informed decision making to be accomplished even when pixmaps are copied to realized (onscreen) windows or other pixmaps.

Abstract: The invention is directed to a method and apparatus for simulating a digital logic circuit simulator. In particular, a block object, representing a component of the digital logic circuit, is instantiated. An event object having a queue is also instantiated. The queue holds an ordered list of destinations, which are representative of the block objects that the event object initiates an action with. When the event object interacts with the block object, this initiates behavior in the block object indicative of behavior of the component in the digital system. The digital logic circuit simulator components, namely the block object and the event object, can be instantiated in a run-time object oriented language, such as the JAVA® language promulgated by Sun Microsystems. The block object can initiate a dynamic addition to the destination queue. Additionally the destination can be another event object. When the destination is another event object, another event object is initiated.

Abstract: A method creates a proxy auto-configuration file for a system including a plurality of proxy servers. The method includes accessing and performing a performance test on each of the plurality of proxy servers, and creating a proxy auto-configuration (PAC) file in response to the performing. The PAC file may be posted on a web server. The method may further include iteratively updating the PAC file by periodically conducting the accessing, the performing, and the creating. The creating the PAC file may include generating a list of a selected number of best-performing proxy servers among the plurality of proxy servers. The performing the performance test may include sending a command to fetch at least one selected web page, receiving the selected web page, and determining an amount of time required to fetch the selected web page.

Abstract: A buffer block allocation table as well as a buffer allocation table may be provided to handle a buffer request in a system management controller. When a buffer request is received, the buffer block allocation table may be scanned entry-by-entry to find an available buffer block. once one its located, it is marked as taken. Then, the corresponding buffer block in the buffer allocation table is scanned entry-by-entry looking for one that is available. If one is found, it is used for the buffer request. If one cannot be found, the system may return to the buffer block allocation table and continue with the next entry. This process may repeat until an available buffer is found.

Abstract: Managing a task in a system management controller may be accomplished by storing information regarding the task in a process control buffer. A state of the task stored in the process control buffer may be examined to determine if it is active. If so, then a task counter contained in the process control buffer can be examined to determine if the task should be run immediately, or at a later time. If it is immediately, the task is immediately executed. If not, then timer fields may be examined to determine precisely when the task should be executed. The task counter may also indicate the number of times the task should be executed, or if it should be executed indefinitely. Thus, the method may be restarted with a new process control buffer if the timer fields are not less than or equal to a current time.

Abstract: A method performs an operation on physical design data stored as data objects in a database. Each data object represents a design figure of an integrated circuit (IC) design laid-out on an IC design area. The method includes (a) dividing the IC design area into a second plurality of sub-areas, (b) assigning an area property to each of the data objects, the area property indicating the sub-areas on which at least part of the corresponding design figure is to be located, (c) selecting a first data object, and (d) conducting an operation involving the first data object and a second data object involving selecting the second data object from a subset of data objects having an area property indicating a sub-area indicated by an area property of the first data object, and performing the operation on the first data object and the second data object.

Abstract: The present invention provides a solution for converting a boundary scan description language (BSDL) file to a hardware verification language (HVL) test program file. The BSDL file is scanned for header information and the header information is stored in a header object. The BSDL file is then scanned for pin information, the pin information corresponding to at least one pin in the BSDL file having a pin location, and stored in a pin object. At least one variable for the HVL test program file is created and bound to one of the pin locations resulting in a binding relationship for each variable. The binding relationships are then stored in a bind object. The present invention is designed to overcome the disadvantages of the prior art.

Abstract: A customized mailbox is provided to customers for placement outside their home. Simple electronics, such as a display, keypad, bar-code reader, and transmitter/receiver may be contained within the mailbox. When parcel delivery is attempted, the deliveryperson may facilitate the notification of the user by, for example, scanning a bar code on the parcel with the bar code reader. Parcel information is then wirelessly forwarded to a service provider. The service provider may forward parcel information a mobile device or other notification mechanism as specified in user preferences. Upon receipt of the parcel delivery information, the user may, through the mobile device or other notification mechanism, approve delivery of the parcel. The service provider may then forward this approval to the electronic mailbox, where an electronic lock may be opened and the deliveryperson may place the parcel in the electronic mailbox.

Abstract: An apparatus for private personal identification number (PIN) management comprises a memory and a PIN comparator in communication with the memory. The PIN comparator is configured to ascertain a first delay period of a preceding PIN. The first delay period is greater than zero if the preceding PIN does not match a validated PIN and the first delay period equals zero if the preceding PIN matches the validated PIN. The PIN comparator is further configured to receive a current PIN after at least the first delay period and delay for a second delay period if the current PIN does not match the validated PIN. The second delay period is greater than the first delay period.