Abstract: A printed circuit board (PCB) having an integrated strain gage. In one embodiment, a PCB includes a component footprint suitable for mounting an electronic component. A strain gage is integrated into the PCB in a location under the component footprint. The strain gage includes at least one electrical conductor that is accessible for resistance measurements.

Abstract: A circuit has been developed that reduces the effective strength of a keeper circuit during an interval in which at least one path of an evaluation circuit is sensitive to a keeper device. The keeper circuit includes a keeper gating device coupled to a keeper device that is responsive to a keeper control. The keeper device is sized to overcome leakage current in the evaluation circuit. In some configurations, the keeper circuit includes a weak keeper device that is minimally sized to overcome noise while the keeper device is effectively disabled. In some configurations, the reduction in effective strength of the keeper circuit occurs before arrival of the fastest signal coupled to a sensitive output path of the evaluation circuit and the effective strength is restored after arrival of the slowest signal coupled to the sensitive output path of the evaluation circuit.

Abstract: A computer system for cycle-based computation includes a processor array, a translation component adapted to translate a cycle-based design, a host computer operatively connected to the processor array and to the translation component, a data connection component interconnecting a plurality of members of the processor array using static routing, a synchronization component enabling known timing relationships among the plurality of members of the processor array, a host service request component adapted to send a host service request from a member of the processor array to the host computer, and an access component adapted to access a portion of a state of the processor array and a portion of a state of the data connection.

Abstract: A method for routing conductors in an integrated circuit design is disclosed, including the steps of determining the number of sensitive conductors requiring placement into quiet track locations, wherein a quiet track location is defined as any track location immediately adjacent to a stable conductor, determining the number of quiet track locations available in said integrated circuit design, and routing one or more sensitive conductors into one or more quiet track locations.

Abstract: Signal state durations, such as the pulse-width, of on-chip signals are often critical to the successful operation of an integrated circuit. The signal state durations measured by on-chip technology provide signal state duration information to an on-chip signal state duration control system. The signal state duration control system uses the information to adjust the signal state duration of an on-chip signal. In one embodiment, the signal state duration of the on-chip signal is the pulse width of the on-chip signal. The signal duration measurement and adjustment system is, for example, useful for measuring the state duration of signals such as self-resetting signals, which are difficult to externally measure and adjust signal state durations using on-chip technology.

Abstract: This functions maintains two trees: a fast access tree referring to memory blocks of a size most often requested, and a general access tree referring to memory blocks of a size less often requested. After satisfying a request for a memory block, the function adjusts the trees to ensure that the fast access tree refers to memory blocks of the size most often requested. By providing such functionality, the function improves its performance over time through self-adaptation.

Abstract: A distributed system provides for separate management of dynamic cluster membership and distributed data. Nodes of the distributed system may include a state manager and a topology manager. A state manager handles data access from the cluster. A topology manager handles changes to the dynamic cluster topology. The topology manager enables operation of the state manager by handling topology changes, such as new nodes to join the cluster and node members to exit the cluster. A topology manager may follow a static topology description when handling cluster topology changes. Data replication and recovery functions may be implemented, for example to provide high availability.

Abstract: Disclosed are novel methods and apparatus for provision of efficient, effective, and/or flexible computer system layout and/or cooling configuration. In accordance with an embodiment of the present invention, a method of cooling a computer system is disclosed. The computer system may include a plurality of heat generating electrical components that require cooling. The method includes: providing at least two cooling fans arranged front to back of the computer system to create a push (inlet) and pull (outlet) airflow to cool the computer system and providing a plurality of temperature sensors located at various locations within the computer system to sense a local temperature.

Abstract: A register window fill technique for a retirement window having an entry size less than a number of fill instructions used in a fill condition is provided. The technique uses modified fill instructions that allow the retirement window to retire a portion of the fill instructions without having to determine whether a remaining portion of the fill instructions will execute without exceptions.

Abstract: Providing a contract between an application server and a resource adapter that allows the application server to manage the lifecycle of the resource adapter. When deploying a resource adapter (or during application server startup), an application server bootstraps a resource adapter instance in an appropriate address space. When a resource adapter is undeployed (or during application server shutdown), the application server notifies the resource adapter instance to stop functioning in order to allow safe unloading. The contract provides a mechanism for an application server to manage the lifecycle of a resource adapter instance, allowing an application server to bootstrap a resource adapter instance during resource adapter deployment or application server startup and to expose some of its useful facilities to the resource adapter instance. It also provides a mechanism to notify the resource adapter instance while it is undeployed or during an orderly shutdown of the application server.

Abstract: The capacitances of one or more inputs/outputs of a circuit are estimated by using an extraction tool (120) to extract information associated with the inputs/outputs from a netlist. The information includes information associated with circuit devices directly connected to the inputs/outputs, particularly information related to device connectivity and the feature sizes of the device. Once the information is extracted, a capacitance determination element (130) aggregates the feature sizes of all the circuit devices connected to each respective input or output, to obtain aggregate feature sizes for each respective input/output. The aggregate feature size is used in determining the total capacitance of the input/output. The total capacitance thus determined can be provided to a timing analysis tool (140), which uses the total capacitance of each input or output to generate a timing model for the circuit.

Abstract: Resource management for controlling allocation of a resource to competing computer processes is achieved through the use of a joining function. A resource manager is responsive to identification of a thread for a first process requesting allocation of the resource, when the resource is already allocated to a thread for a second process, to establish a joining function to the thread for the second process. The joining function is operable to notify the resource manager on termination of the thread for the second process. The resource manager can therefore be operable in response to termination of the thread for the second process to allocate the resource to the first process. The first and second processes can be call handling processes for telecommunications apparatus where the resource manager provides allocation of a telephony resource, such as a modem or network interface, to the competing call handling applications. A telephony interface and the applications can be implemented in the Java™ language.

Abstract: Error detection using data block mapping is provided. One method includes receiving a write request to write a user data block having a first block size, generating an error detection code for the user data block, appending the error detection code to the user data block to form an extended data block, and mapping the extended data block to a plurality of actual data blocks, each actual data block having a block size equal to the first block size.

Abstract: Described is a scheduling system that provides allocation of system resources of one or more processor sets among groups of processes. Each of the process groups is assigned a fixed number of shares, which is the number that is used to allocate system resources among processes of various process groups within a given processor set. The described fair share scheduler considers each processor set to be a separate virtual computer. Different process sets do not share processes, a particular process must execute on a single processor set. In another embodiment of the invention, each process group could be given a separate number of shares for each processor set. Percentage of the resources of the specific processor set allocated to processes of a process group is calculated as a ratio of the shares of the process group on the processor set to the total number of shares of active process groups operating in that set.

Abstract: Improved techniques for representation of objects in a Java™ programming environment are disclosed. The techniques are highly suitable for representation of Java™ objects inside virtual machines, especially those that operate with limited resources (e.g., embedded systems). A cluster of Java™ object representations is disclosed. Each of the Java™ object representations provide a reference to a Java™ object and a reference to the class associated with the Java™ object. Accordingly, a two-tier representation is provided which allows efficient implementation of applications which need to access information regarding both Java™ objects and classes. As a result, quick access to information regarding Java™ objects can be achieved.

Abstract: A garbage collector collects a dynamically allocated heap by employing the train algorithm, in which “car” sections of a heap generation are organized in groups, or “trains.” When a car section comes up for collection, objects that it contains are evacuated if they are referred to by references located in cars not currently being collected. The cars to which they are evacuated belong to the trains that contain the references. The trains form a sequence in which their constituent cars are to be collected, and objects that are directly allocated in the generation are placed into trains that precede some existing train in the collection sequence.

Abstract: One embodiment of the present invention provides a system that facilitates implementing multi-mode specification-driven disassembler. During operation, the disassembler receives a machine-code version of a computer program. In order to disassemble a specific machine-code instruction from this machine-code version, the system compares the machine-code instruction against a set of instruction templates for assembly code instructions to identify a set of matching templates. Next, the system selects a matching template from the set of matching templates based on the state of a mode variable, which indicates a specificity mode for the disassembler. The system then disassembles the machine-code instruction using the operand fields defined by the matching template to produce a corresponding assembly code instruction.

Abstract: One embodiment of the present invention provides a system that facilitates identifying expansion cards installed in a computer system. The system operates by first examining a device tree for the computer system to identify nodes within the device tree that are associated with the computer expansion cards. Next, the system obtains a subset of parameters from the device tree that are associated with the computer expansion cards, and then performs a pattern match between the subset of parameters for each card and entries in an information file to identify each computer expansion card.

Abstract: A method for inserting a prefix, including traversing a trie node block structure to obtain a trie node block in which to insert the prefix, determining whether the trie node block is associated with a hash table, if the trie node block is not associated with a hash table: calculating a set of hash values for a trie node in the trie node block, and populating the hash table using the set of hash values calculated for the trie node, and inserting the prefix in an appropriate location in the hash table using at least one of the set of hash values associated with the trie node.

Abstract: A garbage collector collects at least a generation of a dynamically allocated heap in increments. In each increment, it identifies references located outside a collection set that refer to objects that belong to the collection set, and it evacuates the objects thus referred to before it reclaims the memory space that the collection set occupies. In some collection increments, references to collection-set objects are located both inside and outside the generation. The collector locates all such references, both those inside the generation and those outside it, before it evacuates any objects in response to any of them. By doing so, it is able to reduce the cost of locating references and evacuating objects.