Abstract: When retrieving documents over a network, such as the Internet, the font size imposed by default or by a style sheet is sometimes not the right size for comfortable viewing by a user. A database of font size changes made by a user to particular documents is maintained and used to infer a font size preference for a document. A document is displayed using a recorded preference. If no preference is found for a document, a check is made to determine if a preference has been specified for a different document related to that document by having a common portion of a network address. That is, if a preference had been specified for one chapter of a document having a particular network address, a preference would be inferred for other chapters of the document based on a common portion of a hierarchical address.

Abstract: A method for selecting a candidate to mark as overwritable in the event of a cache miss while attempting to avoid a write back operation. The method includes associating a set of data with the cache access request, each datum of the set is associated with a way, then choosing an invalid way among the set. Where no invalid ways exist among the set, the next step is determining a way that is not most recently used among the set. Next, the method determines whether a shared resource is crowded . When the shared resource is not crowded, the not most recently used way is chosen as the candidate. Where the shared resource is crowded, the next step is to determine whether the not most recently used way differs from an associated source in the memory and where the not most recently used way is the same as an associated source in the memory, the not most recently used way is chosen as the candidate.

Abstract: The present invention integrates data prefetching into a modulo scheduling technique to provide for the generation of assembly code having improved performance. Modulo scheduling can produce optimal steady state code for many important cases by sufficiently separating defining instructions (producers) from using instructions (consumers), thereby avoiding machine stall cycles and simultaneously maximizing processor utilization. Integrating data prefetching within modulo scheduling yields high performance assembly code by prefetching data from memory while at the same time using modulo scheduling to efficiently schedule the remaining operations. The invention integrates data prefetching into modulo scheduling by postponing prefetch insertion until after modulo scheduling is complete. Actual insertion of the prefetch instructions occurs in a postpass after the generation of appropriate prologue-kernel-epilogue code.

Abstract: The present invention is a method and apparatus that implements a snoop protocol in a multiprocessor system without the use of snoop-in and snoop-out logic units. The multiprocessor system includes a number of nodes connected by a bus operated in accordance with a snoop protocol and the MOSI cache coherency protocol. Each node includes a cache memory and a main memory unit including a shared memory region that is distributed in one or more of the cache memories of the nodes in the system. Each node includes a memory access unit having an export cache that stores identifiers associated with data blocks that have been modified by another node. Each data block in the main memory unit is associated with a state bit that indicates whether the data block is valid or invalid. The export cache and the state of each memory data block is used to determine whether a node should transmit a fetched data block to an initiator node in response to a read miss transaction.

Abstract: Arbiter circuits placed between two signal path segments on a semiconductor chip to measure the difference in propagation delay between those paths at their beginning and end. Each arbiter circuit has two inputs, and outputs signals indicating which of its inputs is the first to receive a leading edge of an input transition. External circuitry monitors the arbiter outputs, and accordingly controls the application of the input transitions. By varying the delay of the input signal paths, the relative propagation delay can be determined.

Abstract: The present invention provides software branch prediction filtering for a microprocessor. In one embodiment, a method for a software branch prediction filtering for a microprocessor includes determining whether a branch is “easy” to predict, and predicting the branch using software branch prediction if the branch is easy to predict. Otherwise (i.e., the branch is “hard” to predict), the branch is predicted using hardware branch prediction. Accordingly, more accurate but space-limited hardware branch prediction resources are conserved for hard-to-predict branches.

Abstract: A processor includes a thread switching control logic that performs a fast thread-switching operation in response to an L1 cache miss stall. The fast thread-switching operation implements one or more of several thread-switching methods. A first thread-switching operation is “oblivious” thread-switching for every N cycle in which the individual flip-flops locally determine a thread-switch without notification of stalling. The oblivious technique avoids usage of an extra global interconnection between threads for thread selection. A second thread-switching operation is “semi-oblivious” thread-switching for use with an existing “pipeline stall” signal (if any). The pipeline stall signal operates in two capacities, first as a notification of a pipeline stall, and second as a thread select signal between threads so that, again, usage of an extra global interconnection between threads for thread selection is avoided.

Abstract: The invention provides a method and apparatus for customizing and substituting strokes provided by a standard API. In a preferred embodiment, a stroke interface that encapsulates stroking algorithms and interfaces for stroke calculation is provided by an API. The stroke interface is provided in the form of a class. The use of the stroke interface permits additional algorithms and interfaces to be provided as new classes. This allows developers to customize stroke characteristics and attributes. In a preferred embodiment, a basic stroke class contains standard stroke characteristics of a logical pen. These characteristics include line width, end cap shape, line join style, and dash attributes.

Abstract: Methods, systems, and articles of manufacture consistent with the present invention coordinate distribution of shared memory to threads of control executing in a program by using a cooperative synchronization protocol. The protocol serializes access to memory by competing threads requesting assignment of memory space, while allowing competing threads that have already been assigned memory space, to share access to the memory. A designated area of memory assigns the memory to requesting threads. The protocol is an application level entity and therefore does access the operating system to serialize the memory allocation process.

Abstract: The technology of the present invention pertains to an apparatus and method for implementing a hardware-based performance monitoring mechanism for use in analyzing the behavior of a program module. The apparatus includes probe logic hardware that monitors the program's behavior in executing memory reference instructions. The probe logic hardware generates several probe signals which are transmitted to a performance monitor circuit when certain events occur. In an embodiment of the present invention, these events can be TLB or cache misses. The performance monitor circuit affixes a time stamp to the probe data and stores the time-stamped probe data in a temporary memory device until the data is stored in a magnetic storage device.

Abstract: A parallel fixed-point square root and reciprocal square root computation uses the same coefficient tables as the floating point square root and reciprocal square root computation by converting the fixed-point numbers into a floating-point structure with a leading implicit 1. The value of a number X is stored as two fixed-point numbers. In one embodiment, the fixed-point numbers are converted to the special floating-point structure using a leading zero detector and a shifter. Following the square root computation or the reciprocal square root computation, the floating point result is shifted back into the two-entry fixed-point format. The shift count is determined by the number of leaded zeros detected during the conversion from fixed-point to floating-point format.

Abstract: A graphics system comprises a graphics processor, a sample buffer, and a sample-to-pixel calculation unit. The graphics processor generates samples in response to received stream of graphics data. The sample buffer may be configured to store the samples. The sample-to-pixel calculation unit is programmable to generate a plurality of output pixels by filtering the rendered samples using a filter. A filter having negative lobes may be used. The graphics system computes a negativity value for a first frame. The negativity value measures an amount of pixel negativity in the first frame. In response to the negativity value being above a certain threshold, the graphics systems adjusts the filter function and/or filter support in order to reduce the negativity value for subsequent frames.

Abstract: A dithering system comprising a dithering unit, a storage medium, and an averaging unit. The dithering unit is configured to receive a set of data values, to add dither values to the data values, and to truncate the resultant addition values to L-bit truncated values. The storage medium is configured to store the L-bit truncated values. The averaging unit is configured to read the L-bit truncated values from the storage medium, and to compute an average value using at least a subset of the L-bit truncated values. The dither values may have an average value of approximately one-half. The dither values may approximate a uniform distribution of numbers between −A+½ and A+½, wherein A is greater than or equal to one. Alternatively, the dithering unit may receive a temporal stream of data values, and the average unit may perform a temporal average (e.g. an FIR filter). The dithering system may be incorporated in a graphics system.

Abstract: A method and apparatus for providing plug-in media decoders. Embodiments provide a “plug-in” decoder architecture that allows software decoders to be transparently downloaded, along with media data. User applications are able to support new media types as long as the corresponding plug-in decoder is available with the media data. Persistent storage requirements are decreased because the downloaded decoder is transient, existing in application memory for the duration of execution of the user application. The architecture also supports use of plug-in decoders already installed in the user computer. One embodiment is implemented with object-based class files executed in a virtual machine to form a media application. A media data type is determined from incoming media data, and used to generate a class name for a corresponding codec (coder-decoder) object.

Abstract: The present invention describes a method and system for achieving high availability in a networked computer system. In particular, the method for achieving high-availability is executed in a networked computer system. The networked computer system includes nodes connected by a network. The method includes using high-availability-aware components to represent hardware and software in the networked computer system, managing the components to achieve a desired level of redundancy, and monitoring health of the networked computer system, including health of components and nodes. The method further includes detecting a failure in the networked computer system. Failures detected by the method include failures of a component and/or node. Finally, the method includes recovering from the failure by performing an appropriate failure recovery procedure.

Abstract: A driver may be provided which controls output impedance of a driver which includes within the driver an impedance circuit and slew rate control. Accordingly, a desired output slew rate and a desired output impedance can be advantageously established and maintained over a wide range of variations in operating conditions, manufacturing processes and output voltage levels. Such a driver also advantageously limits any crowbar current, thereby reducing the overall power consumption of the driver with little, if any, degradation of driver performance.

Abstract: A graphical user interface enhances user information when scrolling through a document by determining the amount of relevant information at a particular scrolling location and changing one or more user perceptible system attributes such as color, sound or object displayed to reflect the amount of relevant information. In one approach, a <RELEVANT> tag or marker indicates relevance. Alternatively, adding an attribute to an existing HTML tag such as <STRONG> can indicate relevance. If information received from a search in response to a query contains no relevance indications, relevance markers are added locally.

Abstract: A method of continuously replenishing a four-transistor static RAM storage cell is described. Such method comprises biasing both the back gate terminals and the normal gate terminals of the two bit line coupling transistors in the static RAM storage cell to voltage levels for causing a flow of small compensating currents through such coupling transistors when they are in a standby or non-access condition. Such small compensating currents are supplied to the two storage transistors in the storage cell for replenishing leakage of charge from the parasitic capacitance in the storage cell. The bias voltages are supplied by adaptive bias circuits which adjust the bias voltages to track changes in the leakage of charge from the parasitic cell capacitance.

Abstract: A graphics system capable of super-sampling and performing real-time convolution. The graphics system may comprise a graphics processor, a sample buffer, and a sample-to-pixel calculation unit. The graphics processor receives graphics data and generates a plurality of samples for each of a plurality of frames. The sample buffer stores the samples. The sample-to-pixel calculation unit is operable to generate output pixels by filtering the rendered samples using a filter. A display device then receives and displays the output pixels. A user may observe the displayed image and adjust properties of the filter according to the user's personal visual preferences. A display-monitoring device may be configured to capture the displayed image. The graphics system may then analyze the captured image and, in response to the captured image, perform filter adjustments.

Abstract: Methods and apparatus for implementing state machines as enterprise beans with reliable or transactional timers on an enterprise platform are disclosed. According to one aspect of the present invention, a state machine is arranged to be used within a computing system that supports an enterprise platform. The state machine includes an entity object, a home interface associated with the entity object, and a remote interface associated with the entity object. The home interface is arranged to create, find, and remove entity objects, while the remote interface is arranged to drive the state machine. The entity object is arranged to be deployed in a bean container, which includes a timer. In addition to including a timer, the bean container is arranged to invoke the entity object using the remote. In one embodiment, the timer is transactional.