Abstract: A cluster implements a virtual disk system that provides each node of the cluster access to each storage device of the cluster. The virtual disk system provides high availability such that a storage device may be accessed and data access requests are reliably completed even in the presence of a failure. To ensure consistent mapping and file permission data among the nodes, data are stored in a highly available cluster database. Because the cluster database provides consistent data to the nodes even in the presence of a failure, each node will have consistent mapping and file permission data. A cluster transport interface is provided that establishes links between the nodes and manages the links. Messages received by the cluster transports interface are conveyed to the destination node via one or more links. The configuration of a cluster may be modified during operation.

Abstract: The invention is a method and apparatus for chording. One embodiment of an apparatus comprises a user-wearable support element, in the form of a glove having finger and thumb portions. An output generating element in the form of a switch is provided corresponding to each finger and thumb portion of the glove. An activator is provided for each finger and thumb portion of the glove. In one embodiment, each activator comprises a wire having one end connected to the glove and a second end arranged to activate the switch corresponding to its respective finger or thumb portion. Movement of each finger and thumb into one or more positions causes the respective activator to activate its respective switch. In one embodiment, the outputs generated by the switches are input to a signal controller. The signal controller is arranged to provide a second output dependent upon the inputs from the various switches. In one embodiment, the second output is determined from a map and comprises alphanumeric data.

Abstract: A memory has memory cells arranged in rows and columns. The memory cells of each row are coupled to a word line that is separate from word lines connecting to the memory cells of other rows. Each column has mutually exclusive subsets of memory cells. The memory cells are coupled to bit lines. Each bit line is coupled to a selected mutually exclusive subset of memory cells. The memory cells of a selected row output a cell voltage on the coupled bit lines when the coupled word line is asserted. A multiplexor receives the cell voltages on the bit lines. The multiplexor is responsive to column select signals to select one of the columns as a selected column, and outputs a multiplexor voltage corresponding to the cell voltage of the memory cell of the selected row and the selected column.

Abstract: A driver capable of launching signals into a transmission line and of terminating signals at a receiver end of the transmission line includes within the driver a circuit for controlling the output impedance and a circuit for controlling the output slew rate. Accordingly, a desired output impedance can be advantageously established and maintained over a wide range of variations in operating conditions, manufacturing processes and output voltage levels. Such a driver also advantageously limits any crowbar current, thereby reducing the overall power consumption of the driver with little, if any, degradation of driver performance. The driver includes a pull up circuit coupled to receive at least one of a plurality of control codes. The pull up circuit includes pull up output circuit and an impedance control buffer circuit, a parallel pull up circuit, the parallel pull up circuit and the pull up output circuit being controllable to adjust the impedance of the pull up circuit.

Abstract: A vertical multi-threading processor includes one or more execution pipelines that are formed from a plurality of multiple-bit pipeline register flip-flops. The multiple-bit pipeline register flip-flops supply multiple storage bits. The individual bits of a multiple-bit pipeline register flip-flop store data for one of respective multiple threads or processes. When an executing (first) process stalls due to a stall condition, for example a cache miss, an active bit of the multiple-bit register flip-flop is stalled, removed from activity on the pipeline, and a previously inactive bit becomes active for executing a previously inactive (second) process. All states of the stalled first process are preserved in a temporarily inactive bit of the individual multiple-bit register flip-flop in each pipeline stage.

Abstract: A system and method for circuitry design verification testing using a structure of interface independent classes to provide for rapid prototyping and design modification while maximizing test code re-use. A circuit simulation subsystem is interfaced with a test subsystem. The test subsystem employs a system transaction class for collecting common routines and pointers to device transactions. One or more configuration transaction classes derived from the system transaction class define transactions between functional models within the simulation subsystem and cause instantiation of the respective functional models. Operations are performed on the functional models via pointers to interface independent transaction classes which define interfaces to the devices. The operations are mapped to the current designs of the functional models by subclasses of the interface independent transaction classes.

Abstract: A power distribution sub-system distributed power from n+m (e.g. 3) power supply units within a system unit, where n and m are integers and n power supply units (e.g. 2) are required to power the system. The power supply units are connectable to a common power rail. A current sensor detects a current greater than n*Imax, where Imax is the maximum power output of a power supply unit. The current sensor outputs an overcurrent signal when the sensed current exceeds n*Imax. In response to this overcurrent signal, a controllable shunt operates to shunt the power rail to ground, thereby discharging any stored charge. A power distribution board, which forms part of a power sub-frame assembly, carries the power distribution sub-system. The system unit can be a rack-mountable computer system unit for a telecommunications.

Abstract: One embodiment of the present invention provides a system for asynchronously controlling state information within a circuit. This system includes a first conductor that carries a voltage indicating a state of the circuit, as well as a first drive circuit coupled to the first conductor that is configured to drive the first conductor to a first voltage level to indicate a first state. The system also includes a second drive circuit coupled to the first conductor that is configured to drive the first conductor to a second voltage level to indicate a second state. The system additionally includes a condition input that indicates a condition. The system is configured so that the first drive circuit drives the first conductor to the first voltage level based upon the condition indicated by the condition input.

Abstract: A system for leasing a group membership in a distributed processing system is provided. In accordance with this system, a remote object requests from an activation group a membership in the activation group for a period of time. Responsive to this request, the activation group determines an appropriate lease period during which time the remote object becomes a member of the activation group and runs in the same address space as other objects of the activation group.

Abstract: Event notification in a distributed system using an object maintained in serialized form, referred to as a marshalled object. For event notification, a machine registers with a device to receive notification of particular events within a network, and a marshalled object is transmitted with a registration request.

Abstract: An optimized, superscalar microprocessor architecture for supporting graphics operations in addition to the standard microprocessor integer and floating point operations. A number of specialized graphics instructions and accompanying hardware for executing them are disclosed to optimize the execution of graphics instruction with minimal additional hardware for a general purpose CPU.

Abstract: A computer system employs a hierarchical ring structure for communication. Computer system elements are configured into modules with ring interface hardware, and the modules are coupled to one or more rings. Bridge modules may be included for transmitting between rings in the hierarchy. The rings are time division multiplexed, and each time slot on a ring carries a frame. According to an address carried within the frame, bridge modules determine whether or not to transmit a frame circulating on a source ring onto a target ring. If the address of the frame indicates a module upon the source ring, the bridge module retransmits the frame on the source ring. Otherwise, the bridge module transmits the frame on the target ring. The bridge module operates in this fashion at any level of the hierarchy. The owner of a time slot on a ring is permitted to release the time slot for use by other modules. To reclaim a time slot, the owner marks the time slot owned.

Abstract: A system and method for rapid processing of scene-graph-based data and/or programs is disclosed. In one embodiment, the system may be configured to utilize a scene graph directly. In another embodiment, the system may be configured to generate a plurality of structures and threads that manage the data originally received as part of the scene graph. The structures and threads may be configured to convey information about state changes through the use of messaging. The system may include support for messaging between threads, messaging with time and/or event stamps, epochs to ensure consistency, and ancillary structures such as render-bins, geometry structures, and rendering environment structures. A master control thread may be utilized to manage the allocation of resources and the timing of thread execution.

Abstract: A system, method, and computer-readable medium containing computer programming instructions are disclosed for allowing threads in a multi-threaded process to continue operating when a single offending thread within the process causes a critical signal and crashes. A critical signal directed to a particular multi-threaded process resulting from the execution of an offending thread in the process is handled by a critical signal thread. The critical signal thread is invoked when the process receives a critical signal and prevents the entire process from shutting down because of one bad thread in the process. The critical signal thread terminates the resources and connections associated with the offending thread. It does this without effecting the performance of other non-offending threads in the process thereby preventing the termination of other connections in the process because of illegal or invalid operations of a single thread.

Abstract: A method of remotely executing a computer process between a parent computer initiating the process and a child computer executing the process. In one embodiment the process includes a step of associating objects with representations having specific object bindings dependent on the site of process of execution. The same representation has a first object binding if the process is executed on the parent computer, and a second object binding if the process is executed on the child computer. The set of objects associated with these location dependent representations may include objects resident at both the parent and child computers. Additional objects may be associated with a second set of representations having object bindings dependent upon the network site of process execution to accommodate remote process executions across two or more computer networks. In an alternative embodiment, objects are associated with multiple representations in an ordered merge directory.

Abstract: A method and apparatus for ensuring that code being executed by a data processing system conforms to a platform standard. As an example, one embodiment of the present invention validates Pure Java platform standard conformance of Java programs downloaded from a remote server to ensure that they conform to the “Pure Java” standard. This checking can be performed at the time that the program is downloaded across a network firewall and/or at one or more times during the loading and execution of the program.

Abstract: A distributed budgeting and accounting system is designed to operate with secure token devices. The secure token devices serve both as electronic currency purses and as secure vehicles for authorization. The distributed budgeting and accounting system allows a budget to be defined for an organization. The budget is implemented via the secure token devices by transferring electronic currency tokens representing portions of the budgets to secure token devices associated with different portions of the organization. The funds may be transferred down a hierarchical organization by transferring funds between respective pairs of secure token devices. Once the budget has been fully distributed, members of the organization may spend electronic currency tokens on their secure token devices to cover the cost of using resources. Each card holder of the secure token device may only spend up to the amount provided on the associated secure token device.

Abstract: The present invention is directed to a sorber which is suitable for use in an electromagnetic wave activated sorption system and which is easily adaptable to packaging constraints. One embodiment of the sorber comprises a flexible enclosure having an outer conductor, and inner conductor, a port through which a sorbate can be communicated into and out of said enclosure, and a sorbent in the enclosure which can adsorb the sorbate to form a sorbate/sorbent compound. The enclosure is configured to be coupled to an electromagnetic wave generator so that waves generated by the electromagnetic wave generator propagate through the sorbate/sorbent compound within the enclosure. Another embodiment of the sorber comprises an enclosure which is configured to serve as a structural component.

Abstract: A method and computer graphics system for rendering images using programmable sample positions is disclosed. In one embodiment, the computer graphics system may comprise a graphics processor, a sample buffer, and a sample-to-pixel calculation unit. The graphics processor may be configured to generate a plurality of samples using a sample positioning algorithm selected from a programmable memory or generated by programmable hardware. The sample buffer, which is coupled to the graphics processor, may be configured to store the samples. The sample buffer may be super-sampled and double buffered. The sample-to-pixel calculation unit is programmable to select a variable number of stored samples from the sample buffer to filter into an output pixel. The sample-to-pixel calculation unit performs the filter process in real-time, and may use a number of different filter types.

Abstract: The present invention provides a system that looks up thread-specific computer system parameters from a centralized repository. These thread-specific computer system parameters govern interactions between threads and components within a computer system. The system operates by receiving a request from a thread to look up a thread-specific computer system parameter. In response to this request, the system obtains a thread identifier associated with the thread, and uses the thread identifier to look up the thread-specific computer system parameter from the centralized repository of computer system parameters. Next, the system uses the thread-specific computer system parameter in performing an action for the thread related to operation of a computer system component. For example, the system may use the thread-specific computer system parameter to “power on” or “power off” a board within a server.