Abstract: A concurrent incremental garbage collector where tracking and summarization of modified references is concurrent with application operations. A card table is arranged with write barriers so that an application's modification of objects in memory cards are memorialized in the card table. The collector performs an atomic operation, e.g., a compare-and-swap (CAS), on the card table to detect modified or written to objects. Card table indicators of dirtied cards are reset or emptied and the corresponding dirtied cards are scanned for the modifications and the remembered sets updated. Another CAS is performed on the same card table and if any dirtied cards are indicated the collector preserves the card table with the dirtied indicators and operates on a distant card table. If the CAS succeeds no modifications were made and the collector operates on the next scheduled card table group.

Abstract: A small and power-efficient buffer/mini-cache sources and sinks selected DMA accesses directed to a memory space included in a coherency domain of a microprocessor when cached data in the microprocessor is inaccessible due to any or all of the microprocessor being in a low-power state not supporting snooping. Satisfying the selected DMA accesses via the buffer/mini-cache enables reduced power consumption by allowing the microprocessor (or portion thereof) to remain in the low-power state. The buffer/mini-cache may be operated (temporarily) incoherently with respect to the cached data in the microprocessor and flushed before deactivation to synchronize with the cached data when the microprocessor (or portion thereof) transitions to a high-power state that enables snooping. Alternatively the buffer/mini-cache may be operated in a manner (incrementally) coherent with the cached data.

Abstract: A method for simulating running a software application having a plurality of processes on a computer system being tested. The method includes providing a number of work daemons on the test system, with the number being chosen to be substantially equal to the number of processes in the simulated software application. The method continues with configuring each of the work daemons with a static portion that performs functions on or exercises memory of the test system when the work daemon is run. Each of the work daemons is also configured with a dynamic portion including text segments that are selectively executable when the work daemon is run. The static and dynamic portions simulate operations performed by a corresponding one of the modeled software application processes. The method includes running at least a portion of the configured work daemons on the test system and monitoring performance of the test system.

Abstract: One embodiment of the present invention provides a system that facilitates creating a hierarchical model from a programming language file that includes components. The system operates by obtaining a component from the programming language file. Upon obtaining the component, the system passes an encoder to the component and requests that the component encode itself using the encoder, thereby causing the encoder to generate elements in the hierarchical model. Each element includes an attribute that identifies the component, thereby allowing the component to be subsequently identified by referencing the attribute in the corresponding element in the hierarchical model.

Abstract: One embodiment of the present invention provides a system that facilitates determining a frequency of execution of compiled methods within a virtual machine. The system starts by determining if a compiled method is executing. If so, the system sets a flag corresponding to the compiled method to indicate that the compiled method is executing. Periodically, the system scans the flag and increments the value of a corresponding counter if the flag is set, and then resets the flag. Finally, the system analyzes the value of the counter to determine a frequency of execution of the compiled method.

Abstract: Provided are a method, system, and article of manufacture for processing requests in a server side application. The server side application receives a request in a communications protocol from a client. The server side application modifies the request to create a communications protocol independent request. The server side application generates a response by processing the communications protocol independent request. Subsequently, the server side application sends the generated response in the communications protocol to the client.

Abstract: A generator mechanism for generating an administration framework for server systems. In one embodiment, the administration framework may be generated from meta-information that describes elements of configuration data and relationships among the elements. The mechanism may provide automatic generation of the administration framework. In one embodiment, the administration framework may be a stack on an administration server that includes several layers each including one or more generated components. In one embodiment, the generation mechanism may generate management beans of a management layer, representing business logic of the server; configuration beans of a data representation layer; and a presentation layer for accessing and administering generated components. The data representation layer may provide transparency to the persistent store for the other layers. A production generation of the administration framework may be performed and instances of generated components may be deployed on other servers.

Abstract: In one embodiment, a processor comprises a coherence trap unit and a trap logic coupled to the coherence trap unit. The coherence trap unit is also coupled to receive data accessed in response to the processor executing a memory operation. The coherence trap unit is configured to detect that the data matches a designated value indicating that a coherence trap is to be initiated to coherently perform the memory operation. The trap logic is configured to trap to a designated software routine responsive to the coherence trap unit detecting the designated value. In some embodiments, a cache tag in a cache may track whether or not the corresponding cache line has the designated value, and the cache tag may be used to trigger a trap in response to an access to the corresponding cache line.

Abstract: A method for obtaining a quorum vote by a first node using a quorum cable, wherein the quorum cable comprises a first end connected to the first node and a second end connected to a second node, including determining whether the quorum cable is reserved by the second node using a remote reservation input (RRI) on the first end, if the quorum cable is not reserved by the second node asserting a local reservation input (LRI) on the first end by the first node, monitoring a local reservation output (LRO) on the first end by the first node to determine whether the LRO on the first end is asserted in response to asserting the LRI on the first end, and obtaining the quorum vote by the first node, if the LRO on the first end is asserted.

Abstract: Embodiments of the invention are directed to circuits and techniques for computer processor register integrity checking employing digital roots, and hexadecimal digital roots (HDRs) in particular, to validate the results of arithmetic operations and register moves. These circuits thus provide extra confidence that register operations were correctly executed. A hexadecimal digital root is computed for the result of each register computation and compared to the results of the same computation performed on the HDRs of the operands. The hexadecimal digital root approach may be simply implemented with standard combinatoric logic. Validation is accomplished in a single clock cycle so that there is no added system delay or latency. The circuits and methods described herein have comparatively little impact on processor real estate.

Abstract: Systems, computer implemented methodology, and computer readable media for measuring position error signal differential nonlinearity in timing based servo patterns. A set of two or more reading heads, positioned at various locations along a servo stripe and orientated transverse to the longitudinal motion of the tape, collect PES data concerning servo stripes. A differential between the two reading heads is examined at various locations along the servo stripe of the servo pattern to ascertain differential PES data regarding an area of interests along the servo stripe. Examination of the differential data is thereafter conducted to isolate systematic PES readings from nonsystematic PES readings. The nonlinearity of the systematic PES readings at the various locations along the servo stripe is measured so as provide the ability to compensate for the nonlinear differential PES associated with the non-ideal shape of servo stripes.

Abstract: A multiple-location read, single-location write operation is implemented using transient blocking synchronization support. The multiple-location read, single-location write operation involves first acquiring transient ownership of a memory location to be modified and then acquiring transient ownership of at least one other memory location, the contents of which are read and used to modify the memory location first acquired.

Abstract: Managing physical memory for one or more processes with both a minimum and a maximum amount of physical memory. Memory sets are created, each specifying a number of credits. The total number of credits specified by all memory sets are equal to the total number of pages in physical memory. One or more processes are bound to a memory set. All of the processes bound to a memory set are collectively referred to as the workload of the memory set. Each physical page is accounted for to ensure that each workload can utilize at least the number of physical pages equaling the number of credits in its memory set. Additionally, a workload is permitted to use physical pages that are being explicitly shared by workloads of other memory sets. Accordingly, a workload with both a minimum and a maximum amount of physical memory is specified by its memory set.

Abstract: A graphics system including a frame buffer and a processing unit. The frame buffer contains N slots per pixel. Slots are used to store fragments. Suppose the N slots for a given pixel are occupied. In response to having received (or generated) a new fragment for the pixel, the processing unit may (a) blend the two backmost slots to liberate space for the new fragment, (b) blend the new fragment with the backmost slot in a first order, or, (c) blend the new fragment and the backmost slot in a second order. The choice of (a), (b) or (c) depends on the relationship of the new fragment's z value to the z values of the two backmost slots. The processing unit may be programmably configured to perform multi-pass order independent transparency in either front-to-back order or back-to-front order.

Abstract: A method of generating an embedded file involving embedding a plurality of probe calls into source code to obtain embedded source code, compiling the embedded source code to generate object code including a probe relocation for each of the plurality of probe calls, post processing the object code to obtain a plurality of modified object code, wherein the plurality of modified object code includes object code containing a no-operation instruction in place of the probe relocation and object code containing probe encoding, and linking the plurality of modified object code to obtain an embedded file, wherein the embedded file includes probe encoding.

Abstract: A method and system is disclosed for utilizing an ephemeral encryption or decryption agent so as to preclude access by the ephemeral encryption agent or decryption agent, respectively, to the information being ephemerally encrypted or decrypted. To preclude access by the ephemeral encryption agent, a blinding function is applied to the information prior to forwarding such information to the encryption agent for encryption. To preclude access to the information by the ephemeral decryption agent, a blinding function is applied to the encrypted information prior to forwarding the encrypted information to the decryption agent for decryption. Once the information has been returned, the information is unblinded, leaving an encrypted or decrypted message respectively.

Abstract: A method and mechanism for enabling access to a protected register in a client. A system including multiple clients, such as components and devices, is coupled to a service processor which is configured to manage the system. Clients which are managed by the service processor include control and status registers which are protected from access by unauthorized entities. Access rights for particular registers may be restricted to only the service processor. Clients include a timer which the service processor periodically updates. In the event communication is lost between the service processor and a client, the timer is not updated. In response to detecting the timer was not updated, the client is configured to alter the access rights of the register in order to permit an alternate entity to access the protected register. The service processor may then utilize the alternate entity as a proxy in order to transfer the client state to another client and configure the affected client out of the system.

Abstract: A memory system comprising memory modules including memory chips stacked with switching circuits. A memory controller coupled to the memory modules is configured to initiate memory accesses. When a stacked switching circuit detects the memory access, the switching circuit routes the access to another memory module if the access is not directed to a memory chip of the receiving memory module, or processes the access locally if the access is directed to a memory chip of the receiving memory module. The memory controller and memory modules are coupled via bi-directional serial links. Each memory module may include multiple stacked switching circuits, each of which may be coupled to fewer than all of the memory chips within the memory module. Switching circuits further include circuitry configured to de-serialize data prior to conveyance to a memory chip, and serialize data received from a DRAM chip prior to transmitting the received data.

Abstract: An approach which enables the overhead of performing a task associated with performing a procedure (function) call to be shifted to clients from a reverse proxy server when the reverse proxy server forwards web pages, the content of which may be dynamically created on the clients according to a description (e.g., using Java Script Language). The reverse proxy server may include instructions associated with the description to re-define the procedure call such that the task (in addition to the logic of the pre-defined procedure call) is performed on the clients. For example, with reference to a procedure call containing a URL accessible only within an intranet, the reverse proxy server may insert instructions which cause each client to insert the URL of the reverse proxy server such that any requests for a resource (corresponding to the URL) are passed through the reverse proxy server.

Abstract: A method and system for dynamically generating web based user interfaces. In one embodiment, a method is disclosed for displaying a user interface over a network to a user. The method begins by reading an HTTP request for authentication from a browser associated with the user. The HTTP request comprises credential information associated with the user. Based on the credential information, a first plug-in module from a plurality of plug-in modules is invoked to authenticate the user. Also, each of the plurality of plug-in modules provide similar authentication services. An authentication user interface is dynamically generated based on the HTTP request and configuration properties that are defined by the first plug-in module.