Abstract: A transaction manager may be paused so that the transactions it manages are prevented from making transaction state changes. While the transaction manager is paused, the transactions that the transaction manager is executing may not be allowed to complete. A transaction manager may be configured to obtain permission from a transaction freeze manager in order to transition the state of a transaction. The transaction freeze manager may function as a read/write lock manager controlling locks on a transaction freeze object. In servicing a transaction state transition request, the transaction freeze manager may grant the transaction manager a read lock on the transaction freeze object. In servicing a transaction manager pause request, the transaction freeze manager may grant an administrative entity a write lock on the transaction freeze object.

Abstract: A timing-constrained circuit (e.g., a self-timed circuit) of optimal performance is achieved by allowing the delay of the circuit to be changed dynamically as a function of operating conditions (e.g., operating voltages or temperatures). The delay of timing signals in the timing-constrained circuit for a given operating condition may be selected to have the minimum margin for that operating condition among the available delays to maximize performance over the entire dynamic range of operating conditions.

Abstract: There can be provided a port operable for a PCI Express link. The port can comprise a scheduler operable to determine a next management packet transmission time, and a windower operable to determine a transmission window based upon the next management packet transmission time. The port can also comprise an inserter operable to examine a data packet stream to determine whether a gap therein occurs during the transmission window, and if such a gap does occur to control insertion of a management packet thereinto. Thus transmission efficiency for management packets over the link can be increased.

Abstract: In a system and method for the distribution of identities and reputation on a network, identity and reputation information may be distributed among nodes on a network (e.g. nodes on a peer-to-peer network). Embodiments may allow nodes on the network to evaluate other nodes' reputation using the distributed reputation information. Embodiments may allow nodes to iteratively increase confidence in a determined reputation of a node by determining the reputation of nodes that provide reputation information corresponding to the node. Embodiments may allow nodes to adjust a reputation of other nodes using results of transactions and prior reputations. Determined or adjusted reputation information and/or transaction information may be distributed among the nodes on the network. In one embodiment, transaction information may be divided into segments and the segments may be distributed among the nodes on the network.

Abstract: A method and system for storing and retrieving extensible multi-dimensional display property configurations. In one embodiment, a method is disclosed for the display of content that is configurable to a variety of contextual environments by reading a plurality of settings that are associated with an electronic device requesting content. The plurality of settings defines the contextual environment of the electronic device. The method continues by incorporating the plurality of settings as values in the list of filter criteria. The list of filter criteria is organized in a hierarchical order and specifies the format within which to present the content to be displayed at the electronic device. Thereafter, the method continues by matching the list of filter criteria with a resource to be displayed with the content. The resource is retrieved from memory for ultimate delivery to the electronic device for display.

Abstract: One embodiment of the invention relates to processing communication packets. A communication packet belongs to a communication data structure (called “conn”) which is unique to a connection including the communication packet. The conn also contains an event list which is a sequential list of functions necessary to process the packet. An event list is selected from a database based on the protocol layers necessary to process the packet and typically contains as many functions as there are layers in between. Therefore, each layer has a functional entry point as an event in the event list. The event list identifies a plurality of communication modules specific for the connection and an ordering thereof. The packet is processed through the plurality of modules based on the ordering. The event list is manipulated to enable a module of the plurality of communication modules to enter one of a plurality of its operational states.

Abstract: A method of operating a computer system includes providing a first version of a program in memory and verifying the program prior to program execution. Program verification includes indicating a verification error when a first version of a first program unit implementation is not internally consistent, indicating a verification error when the first version of the first program unit implementation is inconsistent with the version of the program unit API definition file associated with the first version of the first program unit implementation, receiving a second version of the first program unit implementation and a second version of the first program unit implementation is binary compatible with the first version of the first program unit implementation by comparing the first version of the first program unit API definition file and the second version of the first program unit API definition unit.

Abstract: A system and method for reading register contents from a computational pipeline having a plurality of computational units. The system includes a readback bus and a read control unit. The readback bus has a plurality of logic units coupled in a series. Each logic unit couples to a corresponding one of the computational units. The read control unit couples to each of the computational units through a corresponding load line, and is configured to assert a load signal on one of the load lines in response to a register read request. Each of the computational units is configured to transmit a data value from a selected register onto the readback bus in response to detecting an assertion of the load signal on its corresponding load line.

Abstract: A verification mechanism monitors incoming and outgoing traffic between a channel adapter and a switch fabric in an InfiniBandSM system in order to verify that the InfiniBandSM protocol is correctly followed by the channel adapter. The verification mechanism uses a simple hardware-independent interface to query the channel adapter hardware for specific values and completion queue, queue pair and work queue element attributes that are required for verification. The verification mechanism creates a plurality of verification components that monitor incoming and outgoing messages and verify that each of the channel adapter elements correctly follows the protocol. The verification mechanism is controlled by a verification application programming interface (API) that allows different test benches and tests to incorporate InfiniBandSM protocol verification in any test system for use with any hardware.

Abstract: A multi-directional power distribution unit (PDU) provides flexibility in the configuration of a computer system, disk drive array or other enclosure. The power distribution unit may be installed in one orientation for a power feed having a first configuration (e.g., from the front of the enclosure), and may be installed in a second orientation for a power feed in a second configuration (e.g., from the rear of the enclosure). In either orientation, a set of external power connectors couples to one or more external power feeds. Depending on the orientation, either a first or second internal connector will interface with the system or enclosure (e.g., a midplane, a power supply). The PDU may include circuitry for filtering electrical power and may also include a heat sink.

Abstract: A portable telephone provides a graphical user interface (GUI) using a high-resolution display. The GUI provides a Universal Mailbox for storing both electronic mail and voicemail messages, either of which can be accessed by a user from the same display screen. An automatic reply feature allows a user to initiate an outgoing reply to a received message with the touch of a button. For a reply to a voicemail message, the GUI accesses Caller ID information to automatically identify and dial out to the phone number of the sender of the original message. For an electronic mail reply, the GUI automatically displays a reply form addressed to the source address. Reply forms may be generic, custom designed for a specific source address, or provided by the sender. An advanced call control feature automatically checks an outgoing telephone number against a database to determine whether the phone number is currently appropriate.

Abstract: A look-up switch accelerator which includes an associative memory for storing information associated with one or more look-up switch statements. For each look-up switch statement, this information includes a look-up switch identifier value, a plurality of match values and a corresponding plurality of jump offset values. The look-up switch accelerator also includes circuitry for determining whether a current instruction corresponds to a look-up switch statement stored in the memory, circuitry for determining whether a current match value associated with the current instruction corresponds with one of the match values stored in the memory, and circuitry for accessing a jump offset value from the memory when the current instruction corresponds to a look-up switch statement stored in the memory and the current match value corresponds with one of the match values stored in the memory (wherein the accessed jump offset value corresponds with the current match value).

Abstract: A video server is taught which is capable of outputting a plurality of video streams simultaneously. Each video stream is synchronized at two levels of synchronization: coarse-grain and fine-grain. The coarse-grain synchronization is carried out in software over a plurality of packets of data, and the fine-grain synchronization carried out using the network clock. By utilizing both coarse-grain and fine-grain synchronization as taught by this invention, drift and jitter are controlled, providing accurate presentation of constant bit rate data to a receiving device. As another feature of this invention, a bit pump is utilized which includes header information such as constant bit rate information, and information regarding the rates associated with the coarse-grain and fine-grain synchronization. By utilizing this preinitialized header information, CPU demands are reduced as compared with prior art systems in which the CPU must look up timing information from the data to be transmitted.

Abstract: In a video server hard disk storage unit, video layout ensures average case bandwidth and case seek time during bounded-time information transfers, to maximize access of users S. The storage unit includes D hard disks whose platters are divided into Z zones. Each movie is divided into i blocks and is striped across all D disks such that movie block i is stored on disk (i mod D). In one embodiment, movie block i is placed in zone (i/D) mod Z of disk (i mod D). User streams are organized into slots containing N=S/D streams and the number of streams in each slot accessing a zone is .ltoreq.(N/Z). Seeking is to the nearest end of a set of accesses, where total seek time for a set of N accesses is .ltoreq.N*seek (1.5/N). Preferably two storage buffers/stream are used. Admission policy permits stream assignment to any slot, but streams do not transfer until the needed data block is on the disk needed by the other streams in the slot, and until the block is in the proper disk zone.

Abstract: A low-power, logic signal level converter includes a CMOSFET current mirror differential amplifier with a current control element for providing a level-converted output logic signal in response to an input logic signal while ensuring that virtually no DC current is drawn during steady-state circuit operations. The CMOSFET current mirror differential amplifier includes a PMOSFET current mirror driven by NMOSFET pull-down transistors with a DC current-blocking PMOSFET between them. The interposed PMOSFET blocks DC current flow during steady-state circuit operation without adversely affecting the line driving capacity of the current mirror differential amplifier during logic signal transitions.

Abstract: In a distributed computing environment, an apparatus and method for a federated Naming System which can resolve Composite Names comprised of Names from an arbitrary number of disparate Naming Systems. A syntax for Composite Names is defined as well as necessary operations to directly resolve such Composite Names without the need for customized agents or gateways.