Abstract: A method for updating the contents of a BIOS ROM includes disconnecting a host system from the BIOS ROM, transferring data from a service processor to the BIOS ROM, and updating the contents of the BIOS ROM using the transferred data. A BIOS update system for a computer system, includes a BIOS ROM containing BIOS instructions, a service processor that contains update data for the contents of the BIOS ROM, an LPC bus that transfers the update data from the service processor to the BIOS ROM, and quick switches that disconnect a host system from the LPC bus.

Abstract: A configuration manager federated bean is provided for each host computer in the three-tiered management system. The configuration manager federated bean for a host computer is contacted by federated beans that manage each of the data services when a data service starts and stops using a data storage volume associated with the host computer. The configuration manager bean maintains persistent configuration information for each data service. In one embodiment, configuration manager beans can operate in a clustered environment where several beans store configuration information in a single storage area. Each of the beans implements an arbitration protocol so that only one bean writes to the storage area at any given time.

Abstract: A multi-threaded memory system including a plurality of entries, each one of the plurality of entries including a plurality of threads, each one of the plurality of threads including an active cell and a shared read cell. The shared read cell has an output coupled to a read bit line and a corresponding plurality of inputs coupled to an output of the corresponding active cells in each one of the plurality of threads. A multi-threaded memory system is also described.

Abstract: A method for communicating across first and second frequency domains of an integrated microchip is provided. The method initiates with determining a clock ratio between the first frequency domain and the second frequency domain. The first frequency domain is associated with a faster clock cycle. Then, a synchronizing signal based upon the clock ratio is generated. The synchronizing signal coordinates communication of data between the first and second frequency domains. Next, the data is transferred between respective frequency domains according to the synchronizing signal. A microchip and a system enabling synchronous data transfer across different frequency domains are also provided.

Abstract: A method for detecting tampered program data comprising at least one program unit includes receiving a request for use of the at least one program unit, computing a first fingerprint over stored data associated with the at least one program unit and determining whether the stored data is valid based at least in part on whether the first fingerprint matches a second fingerprint. The second fingerprint is computed over the stored data prior to receiving the request for use of the at least one program unit.

Abstract: A clock generation and control circuit to debug an integrated circuit includes a multiplexer connected to a set of input lines that carry a set of clock signals. The multiplexer selects one of the input lines in response to a select signal generated by a decode circuit. A control circuit provides input signals to the decode circuit. The control circuit specifies a disabled output clock signal in response to a stop signal applied to a single external pin of the integrated circuit. Alternately, the control circuit specifies a disabled output clock signal through a test access port of the integrated circuit. Debug operations are executed while the output clock signal is disabled.