Abstract: A hazard control circuit for a cache controller that prevents overwriting of modified cache data without write back. The cache controller controls a non-blocking, N-way set associative cache that uses a write-back cache-coherency protocol. The hazard control circuit prevents data loss by deferring assignment until after completion of a pending fill for that way. The hazard control circuit of the present invention includes a transit hazard buffer, a stall assertion circuit and a way assignment circuit.
Type:
Grant
Filed:
April 19, 1999
Date of Patent:
September 4, 2001
Assignee:
Sun Mocrosystems, Inc.
Inventors:
Anuradha N. Moudgal, Belliappa M. Kuttanna