Patents Assigned to SunEdison Semiconductor Limited
  • Publication number: 20190057897
    Abstract: A method is provided for preparing a semiconductor-on-insulator structure comprising a silicon oxynitride layer having a gradient oxygen concentration.
    Type: Application
    Filed: March 3, 2017
    Publication date: February 21, 2019
    Applicant: SUNEDISON SEMICONDUCTOR LIMITED
    Inventor: Sasha Joseph Kweskin
  • Patent number: 9951440
    Abstract: An method for producing a silicon ingot includes melting polycrystalline silicon in a crucible enclosed in a vacuum chamber to form a melt, generating a cusped magnetic field within the vacuum chamber, dipping a seed crystal into the melt, withdrawing the seed crystal from the melt to pull a single crystal that forms the silicon ingot, wherein the silicon ingot has a diameter greater than about 150 millimeters (mm), and simultaneously regulating a plurality of process parameters such that the silicon ingot has an oxygen concentration less than about 5 parts per million atoms (ppma). The plurality of process parameters include a wall temperature of the crucible, a transport of silicon monoxide (SiO) from the crucible to the single crystal, and an evaporation rate of SiO from the melt.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: April 24, 2018
    Assignee: SunEdison Semiconductor Limited
    Inventors: Soubir Basak, Carissima Marie Hudson, Gaurab Samanta, Jae-Woo Ryu, Hariprasad Sreedharamurthy, Kirk D. McCallum, HyungMin Lee
  • Patent number: 9939511
    Abstract: A method of preparing an iron-implanted semiconductor wafer for use in surface photovoltage iron mapping and other evaluation techniques. A semiconductor wafer is implanted with iron through the at least two different regions of the front surface of the semiconductor at different iron implantation densities, and the iron-implanted semiconductor wafer is annealed at a temperature and duration sufficient to diffuse implanted iron into the bulk region of the semiconductor wafer.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: April 10, 2018
    Assignee: SunEdison Semiconductor Limited
    Inventors: Igor Rapoport, Robert James Crepin, Patrick Alan Taylor
  • Patent number: 9459935
    Abstract: A computing device is configured to execute a first instance of a single-threaded script engine in a first thread associated with a first execution context, wherein the first instance of the single-threaded script engine accesses at least one shared script object through a first reference counted script base value object. The computing device is also configured to concurrently execute a second instance of the single-threaded script engine in a second thread_associated with a second execution context, wherein the second instance of the single-threaded script engine accesses the at least one shared script object through a second reference counted script base value object. The script engine does not switch between the execution contexts.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: October 4, 2016
    Assignee: SunEdison Semiconductor Limited
    Inventor: Benno Orschel
  • Patent number: 9343379
    Abstract: This invention generally relates to a process for detecting grown-in-defects in a semiconductor silicon substrate. The process includes contacting a surface of the semiconductor silicon substrate with a gaseous acid in a reducing atmosphere at a temperature and duration sufficient to grow grown-in -defects disposed in the semiconductor silicon substrate to a size capable of being detected by an optical detection device.
    Type: Grant
    Filed: October 4, 2011
    Date of Patent: May 17, 2016
    Assignee: SunEdison Semiconductor Limited
    Inventors: Jeffrey L. Libbert, Lu Fei
  • Patent number: 9317912
    Abstract: Methods and systems for use in detecting an air pocket in a single crystal material are described. One example method includes providing a matrix including a plurality of data units, the plurality of data units including image data related to a region of interest of the single crystal material; defining a first half and a second half of the matrix based on a first axis passing through the center of the matrix; determining, by a processor, a difference between each data unit of the first half and a corresponding data unit of the second half; calculating, by the processor, a first index value based on the determined differences; and identifying an air pocket within the single crystal material based on the first index value and a predetermined threshold.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: April 19, 2016
    Assignee: SunEdison Semiconductor Limited
    Inventor: John F. Valley
  • Patent number: 9281233
    Abstract: A method of preparing a monocrystalline donor substrate, the method comprising (a) implanting helium ions through the front surface of the monocrystalline donor substrate to an average depth D1 as measured from the front surface toward the central plane; (b) implanting hydrogen ions through the front surface of the monocrystalline donor substrate to an average depth D2 as measured from the front surface toward the central plane; and (c) annealing the monocrystalline donor substrate at a temperature sufficient to form a cleave plane in the monocrystalline donor substrate. The average depth D1 and the average depth D2 are within about 1000 angstroms.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: March 8, 2016
    Assignee: SunEdison Semiconductor Limited
    Inventors: Jeffrey L. Libbert, Michael John Ries
  • Patent number: 9159596
    Abstract: Apparatus and methods for mechanically cleaving a bonded wafer structure are disclosed. The apparatus and methods involve clamps that grip the bonded wafer structure and are actuated to cause the bonded structure to cleave.
    Type: Grant
    Filed: October 29, 2012
    Date of Patent: October 13, 2015
    Assignee: SunEdison Semiconductor Limited
    Inventors: Gregory A. Young, Jeffrey L. Libbert
  • Patent number: 9129919
    Abstract: Processes for the treatment of silicon wafers to form a high density non-uniform distribution of oxygen precipitate nuclei therein such that, upon being subjected to the heat treatment cycles of essentially any arbitrary electronic device manufacturing process, the wafers form oxygen precipitates in the bulk and a precipitate-free zone near the surface are disclosed. The processes involve activation of inactive oxygen precipitate nuclei by performing heat treatments between about 400° C. and about 600° C. for at least about 1 hour.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: September 8, 2015
    Assignee: SunEdison Semiconductor Limited
    Inventors: Robert J. Falster, Vladimir V. Voronkov, Marco Cornara, Daniela Gambaro, Massimiliano Olmo
  • Patent number: 8940094
    Abstract: A method of fabricating a semiconductor processing device includes providing a susceptor including a substantially cylindrical body portion having opposing upper and lower surfaces. The body portion has a diameter larger than a wafer diameter. The method also includes providing a set of holes circumferentially disposed at a first susceptor diameter, the set of holes being evenly spaced with respect to adjacent holes and extending through the upper and lower surfaces in an area. The first susceptor diameter is larger than the wafer diameter, and holes are omitted along the first diameter in a set of predetermined orientations.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: January 27, 2015
    Assignee: SunEdison Semiconductor Limited
    Inventors: John Allen Pitney, Manabu Hamano
  • Patent number: 8857214
    Abstract: Methods for producing crucibles for holding molten material that contain a reduced amount of gas pockets are disclosed. The methods may involve use of molten silica that may be outgassed prior to or during formation of the crucible. Crucibles produced from such methods and ingots and wafers that are produced from crucibles with a reduced amount of gas pockets are also disclosed.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: October 14, 2014
    Assignee: SunEdison Semiconductor Limited
    Inventors: Steven L. Kimbel, Harold W. Korb, Richard J. Phillips, Shailendra B. Rathod
  • Patent number: 8859393
    Abstract: Methods and systems are disclosed for performing a passivation process on a silicon-on-insulator wafer in a chamber in which the wafer is cleaved. A bonded wafer pair is cleaved within the chamber to form the silicon-on-insulator (SOI) wafer. A cleaved surface of the SOI wafer is then passivated in-situ by exposing the cleaved surface to a passivating substance. This exposure to a passivating substance results in the formation of a thin layer of oxide on the cleaved surface. The silicon-on-insulator wafer is then removed from the chamber. In other embodiments, the silicon-on-insulator wafer is first transferred to an adjoining chamber where the wafer is then passivated. The wafer is transferred to the adjoining chamber without exposing the wafer to the atmosphere outside the chambers.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: October 14, 2014
    Assignee: SunEdison Semiconductor Limited
    Inventors: Michael J. Ries, Dale A. Witte, Anca Stefanescu, Andrew M. Jones
  • Patent number: 8853054
    Abstract: A method is provided for preparing multilayer semiconductor structures, such as silicon-on-insulator wafers, having reduced warp and bow. Reduced warp multilayer semiconductor structures are prepared by forming a dielectric structure on the exterior surfaces of a bonded pair of a semiconductor device substrate and a semiconductor handle substrate having an intervening dielectric layer therein. Forming a dielectric layer on the exterior surfaces of the bonded pair offsets stresses that may occur within the bulk of the semiconductor handle substrate due to thermal mismatch between the semiconductor material and the intervening dielectric layer as the structure cools from process temperatures to room temperatures.
    Type: Grant
    Filed: March 6, 2012
    Date of Patent: October 7, 2014
    Assignee: SunEdison Semiconductor Limited
    Inventors: Guoqiang Zhang, Jeffrey L. Libbert
  • Patent number: 8846493
    Abstract: Silicon on insulator structures having a high resistivity region in the handle wafer of the silicon on insulator structure are disclosed. Methods for producing such silicon on insulator structures are also provided. Exemplary methods involve creating a non-uniform thermal donor profile and/or modifying the dopant profile of the handle wafer to create a new resistivity profile in the handle wafer. Methods may involve one or more SOI manufacturing steps or electronic device (e.g., RF device) manufacturing steps.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: September 30, 2014
    Assignee: SunEdison Semiconductor Limited
    Inventors: Jeffrey L. Libbert, Lu Fei, Robert W. Standley
  • Patent number: 8833564
    Abstract: A method of removing dust from granular polysilicon includes introducing a stream of granular polysilicon, dispersing the longitudinal stream of granular polysilicon by redirecting the stream into a radially outward flow having a circular pattern, and introducing a counter flow of gas in an opposite direction to that of the longitudinal stream of granular polysilicon to contact the radially outward flow to separate the dust from the granular polysilicon.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: September 16, 2014
    Assignee: SunEdison Semiconductor Limited
    Inventors: Seok-Min Yun, Seong-Su Park, Se-Myung Kim, Won-Jin Choi, Woo-Jin Yoon
  • Patent number: 8796116
    Abstract: Methods for producing silicon on insulator structures with a reduced metal content in the device layer thereof are disclosed. Silicon on insulator structures with a reduced metal content are also disclosed.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: August 5, 2014
    Assignee: SunEdison Semiconductor Limited
    Inventors: Alexis Grabbe, Larry Flannery