Abstract: A method is provided for preparing a semiconductor-on-insulator structure comprising a multilayer dielectric layer.

Abstract: The disclosure is directed to a method to recover the gate oxide integrity yield of a silicon wafer after rapid thermal anneal in an ambient atmosphere comprising a nitrogen containing gas, such as NH3 or N2. Generally, rapid thermal anneals in an ambient atmosphere comprising a nitrogen containing gas, such as NH3 or N2 to thereby imprint an oxygen precipitate profile can degrade the GOI yield of a silicon wafer by exposing as-grown crystal defects (oxygen precipitate) and vacancies generated by the silicon nitride film. The present invention restores GOI yield by stripping the silicon nitride layer, which is followed by wafer oxidation, which is followed by stripping the silicon oxide layer.

Abstract: A method is provided for preparing a semiconductor-on-insulator structure comprising a multilayer dielectric layer.

Abstract: The disclosure is directed to a method to recover the gate oxide integrity yield of a silicon wafer after rapid thermal anneal in an ambient atmosphere comprising a nitrogen containing gas, such as NH3 or N2. Generally, rapid thermal anneals in an ambient atmosphere comprising a nitrogen containing gas, such as NH3 or N2 to thereby imprint an oxygen precipitate profile can degrade the GOI yield of a silicon wafer by exposing as-grown crystal defects (oxygen precipitate) and vacancies generated by the silicon nitride film. The present invention restores GOI yield by stripping the silicon nitride layer, which is followed by wafer oxidation, which is followed by stripping the silicon oxide layer.

Abstract: A method is provided for preparing a semiconductor-on-insulator structure comprising a silicon oxynitride layer having a gradient oxygen concentration.

Abstract: A feed assembly supplies polysilicon to a growth chamber for growing a crystal ingot from a melt. An example system includes a housing having support rails for receiving one of a granular tray and a chunk tray and a feed material reservoir positioned above the support rails to selectively feed one of either the granular tray or the chunk tray. A valve mechanism and pulse vibrator are also disclosed.

Abstract: A system for preventing an unsafe operation of at least one machine communicatively coupled to a computing device. The system includes the computing device which includes a processor coupled to a memory. The memory contains processor-executable instructions that, when executed, cause the computing device to perform the steps of storing, in the memory, a first state of a first machine of the at least one machine, generating a first pending output to be issued to the first machine, determining whether an unsafe condition would result if the first pending output is issued to the first machine in the first state, and issuing the first pending output upon determining that issuing the first pending output would not result in an unsafe condition and blocking the first pending output from being issued upon determining that issuing the first pending output would result in an unsafe condition.

Abstract: A method performs phase shift interferometry to detect irregularities of a surface of a wafer after the wafer has been placed into an interferometer and while the wafer is vibrating. Additionally, a system and a non-transitory computer-readable storage medium have computer-executable instructions embodied thereon for performing phase shift interferometry to detect irregularities of a surface of a wafer after the wafer has been placed into an interferometer and while the wafer is vibrating.

Abstract: A method is provided for preparing a semiconductor-on-insulator structure comprising a sacrificial layer.

Abstract: A method for controlling temperatures in an epitaxial reactor for use in a wafer-production process is provided. The method is implemented by a computing device coupled to a memory. The method includes transmitting, to a heating device in a first zone of the epitaxial reactor, an output power instruction representing a base output power. The method additionally includes determining an actual time period for a temperature in the first zone of the epitaxial reactor to reach a target temperature, determining a difference between the actual time period and a reference time period, determining an output power offset based on the difference, and storing the output power offset in the memory in association with the heating device.

Abstract: An method for producing a silicon ingot includes melting polycrystalline silicon in a crucible enclosed in a vacuum chamber to form a melt, generating a cusped magnetic field within the vacuum chamber, dipping a seed crystal into the melt, withdrawing the seed crystal from the melt to pull a single crystal that forms the silicon ingot, wherein the silicon ingot has a diameter greater than about 150 millimeters (mm), and simultaneously regulating a plurality of process parameters such that the silicon ingot has an oxygen concentration less than about 5 parts per million atoms (ppma). The plurality of process parameters include a wall temperature of the crucible, a transport of silicon monoxide (SiO) from the crucible to the single crystal, and an evaporation rate of SiO from the melt.

Abstract: A method of preparing an iron-implanted semiconductor wafer for use in surface photovoltage iron mapping and other evaluation techniques. A semiconductor wafer is implanted with iron through the at least two different regions of the front surface of the semiconductor at different iron implantation densities, and the iron-implanted semiconductor wafer is annealed at a temperature and duration sufficient to diffuse implanted iron into the bulk region of the semiconductor wafer.

Abstract: Apparatus and methods for mechanically cleaving a bonded wafer structure are disclosed. The apparatus and methods involve clamps that grip the bonded wafer structure and are actuated to cause the bonded structure to cleave.

Abstract: A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm; a semiconductor nitride layer in contact with the semiconductor handle substrate, the semiconductor nitride layer selected from the group consisting of aluminum nitride, boron nitride, indium nitride, gallium nitride, aluminum gallium nitride, aluminum gallium indium nitride, aluminum gallium indium boron nitride, and combinations thereof; a dielectric layer in contact with the semiconductor nitride layer; and a semiconductor device layer in contact with the dielectric layer.

Abstract: A method is provided for preparing a high resistivity silicon handle substrate for use in semiconductor-on-insulator structure. The handle substrate is prepared to comprise thermally stable charge carrier traps in the region of the substrate that will be at or near the buried oxide layer (BOX) of the final semiconductor-on-insulator structure. The handle substrate comprising the stable carrier traps is manufactured by hydrogen ions implantation occurring using at least two different energies, followed by a 2-step thermal treatment. The thermally stable defect structures prepared thereby is stable to anneal at temperatures of at least 1180° C. The defect structure comprises 3-dimensional network of nano-cavities interconnected by dislocations. This wafer can be used as a handle wafer for fabricating silicon-on-insulator (SOI) wafers and further fabricating radio frequency (RF) semiconductor devices.

Abstract: A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm; a silicon dioxide layer on the surface of the semiconductor handle substrate; a carbon-doped amorphous silicon layer in contact with the silicon dioxide layer; a dielectric layer in contact with the carbon-doped amorphous silicon layer; and a semiconductor device layer in contact with the dielectric layer.

Abstract: A cost effective process flow for manufacturing semiconductor on insulator structures is parallel is provided. Each of the multiple semiconductor-on-insulator composite structures prepared in parallel comprises a charge trapping layer (CTL).

Abstract: A method of preparing a single crystal semiconductor handle wafer in the manufacture of a semiconductor-on-insulator device is provided. The single crystal semiconductor handle wafer is prepared to comprise a charge trapping layer, which is oxidized. The buried oxide layer in the resulting semiconductor-on-insulator device comprises an oxidized portion of the charge trapping layer and an oxidized portion of the single crystal semiconductor device layer.

Abstract: A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, an optionally relaxed semiconductor layer comprising silicon, germanium, or silicon germanium, an optional polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer.

Abstract: A method of preparing a single crystal semiconductor handle wafer in the manufacture of a silicon-on-insulator device is provided. The method comprises forming a multilayer of passivated semiconductors layers on a dielectric layer of a high resistivity single crystal semiconductor handle wafer. The method additionally comprises forming a semiconductor oxide layer on the multilayer of passivated semiconductor layers. The multilayer of passivated semiconductor layers comprise materials suitable for use as charge trapping layers between a high resistivity substrate and a buried oxide layer in a semiconductor on insulator structure.