Abstract: The present disclosure discloses a method and circuit for accessing a write data path of an on-chip storage control unit. The method includes: transmitting, by the write data path interface, the write address and the write data to an address conversion unit; transmitting, by the address conversion unit, a target address and the write data to a plurality of storage control units, and determining, by the address conversion unit, a target storage control unit; obtaining, by the address conversion unit, a feedback signal of the target storage control unit, and transmitting, by the address conversion unit, the feedback signal to the target controller; and storing the write data.

Abstract: A data transmission method includes: obtaining a target data packet to be stored, the target data packet including an address of the target data packet; determining, from predetermined N parallel-to-serial units based on the address of the target data packet, a target parallel-to-serial unit corresponding to the target data packet, the N parallel-to-serial units being connected to N storage control units in one-to-one correspondence; and transmitting, by the target parallel-to-serial unit, the target data packet to a target storage control unit, and storing, by the target storage control unit, the target data packet in a corresponding storage unit. The target storage control unit is a storage control unit, connected to the target parallel-to-serial unit, of the N storage control units. The target parallel-to-serial unit is configured to divide the target data packet into a plurality of data sub-packets.

Abstract: A DRAM refresh circuit and refresh method, and a proof-of-work chip. The DRAM refresh circuit comprises a row address recording unit, which is configured to record a row that has been accessed in a DRAM within the current refresh cycle; a refresh driving unit, which is configured to be called to perform a refresh operation; and a refresh control unit, which is configured to call, when the refresh control unit is triggered to perform refreshing and according to a record in the row address recording unit, the refresh driving unit to refresh a row that is not accessed in the DRAM within the current refresh cycle.

Abstract: A proof-of-work operation method, a proof-of-work chip, and an upper computer. The proof-of-work chip comprises: a central control unit, which is configured to receive DAG data sent by an upper computer, an external DAG processing unit, which is configured to store the DAG data in a storage unit; the storage unit, which is configured to store the DAG data; and a calculation unit, which is configured to perform a proof-of-work operation according to the stored DAG data.