Abstract: A method of sampling phase calibration and a device thereof is suitable for an analog-to-digital converter and phase lock loop (ADC-PLL). The ADC-PLL conducts sampling on a periodic analog signal according to a sampling phase so as to produce a plurality of digital signals. The sampling phase calibration device includes a storage unit, a motion-detecting unit and a control unit. The motion-detecting unit is to calculate the number of motion data corresponding to a sampling phase. The control unit is coupled to the motion-detecting unit for changing the sampling phase so as to obtain the number of motion data corresponding to each sampling phase and selecting the sampling phase corresponding to the minimum number of motion data as an optimal sampling phase. The ADC-PLL can correctly sample an analog signal by using the optimal sampling phase and reduce the influence of clock jitter to the minimum.

Abstract: A rapid screen control input system includes a display device and a remote control. The display device displays a window with a content, and a cursor. The remote control has a plurality of keys, and a set of directional keys which includes a right directional key, a left directional key, an up directional key, and a down directional key for providing a start key and a stop key. The remote control is used for remotely controlling the display device and the cursor. When the cursor is moved to a position within the window, the at least one window can be resized or moved, or the content of the window can be moved, by means of activating the start key and pressing at least one of the directional keys.

Abstract: A system for processing a television (TV) picture-out-picture (POP) includes a line buffer, a first multiplexer, an image processing engine, a scaling engine and a timing generator. The line buffer receives partial pixels of a first picture and partial pixels of a second picture. The first multiplexer selects the partial pixels of the first and second picture as an output. The image processing engine performs an image processing on the partial pixels output by the first multiplexer to thereby produce processed pixels. The scaling engine performs a scaling operation on the processed pixels to thereby produce scaled pixels. The timing generator produces a timing signal for the image processing engine and the scaling engine and produces enable signals respectively for the first picture and the second picture. The image processing engine and the scaling engine process the partial pixels of the first or second picture in multiplexing.

Abstract: A data recovery method includes the following steps. Firstly, plural sampling values are classified into a first group, a second group, a third group and a fourth group. A first channel estimation value and a second channel estimation value are generated according to the sampling values of the second group and the third group. A judging step is performed to judge whether a first sampling value of the first group is lower than the first channel estimation value or a second sampling value of the fourth group is higher than the second channel estimation value. If the judging condition is satisfied, a polarity of the first sampling value or the second sampling value is changed and then the plural sampling values are outputted. If the judging condition is not satisfied, the plural sampling values are directly outputted.

Abstract: A circuit for generating a tracking error signal is provided. The circuit includes a digitizing circuit, a short signal removing circuit and phase comparator. The digitizing circuit receives first and second pick-up signals outputted from a pick-up head, and respectively compares the first and the second pick-up signals with a reference signal to obtain a first digital signal and a second digital signal. The short signal removing circuit is used for removing pulses in the first and the second digital signals, wherein the pulse width of the removed pulses are shorter than a preset time, and the first and second digital without the removed pulses are respectively served as a first determining signal and a second determining signal. The phase comparator receives the first determining signal and the second determining signal for outputting the tracking error signal according to a phase difference between the first and the second determining signals.

Abstract: A control system for memory access includes a system memory access command buffer, a memory access command parallel processor, a DRAM command controller and a read data buffer. The system memory access command buffer stores plural system memory access commands. The memory access command parallel processor is connected to the system memory access command buffer for fetching and decoding the system memory access commands to plural DRAM access commands, storing the DRAM access commands in DRAM bank command FIFOs, and performing priority setting according to a DRAM bank priority table. The DRAM command controller is connected to the memory access command parallel processor and a DRAM for receiving the DRAM access commands, and sending control commands to the DRAM. The read data buffer is connected to the DRAM command controller and the system bus for storing the read data and rearranging a sequence of the read data.

Abstract: A system for detecting poor video editing detects a television (TV) image signal. When a TV image originates from a film signal rather than a video signal, a de-interlacing device performs a de-interlacing at a film signal mode to thereby increase a vertical resolution of a TV image signal. A sawtooth detector can detect a poor video editing, which causes a sawtooth occurrence to TV image signals, on an unbroadcasted TV image signal. Accordingly, the poor video editing is found in advance. Also, the invention uses a scene change in combination with the sawtooth detector to thereby avoid a poor edited image and obtain a preferred image quality.

Abstract: A method for detecting a typical defect area on a disc track includes the following steps. Firstly, a source signal is provided. Then, first and second signals are generated according to the source signal. The first and second signals are held at the peak level of the source signal and respectively decreased at first and second drop rates. Then, first and second threshold values are subtracted from the first and second signals to generate first and second slice signals, respectively. Afterwards, the source signal is compared with either the first slice signal or the second slice signal. When the first slice signal is larger than the source signal, a typical defect signal is changed from a first level to a second level. Whereas, the typical defect signal is changed from the second level to the first level when the second slice signal is smaller than the source signal.

Abstract: The invention provides a system and method for controlling multimedia communication quality in a handheld device. The handheld device receives and transmits multimedia data via a wireless network. First, the predetermined video coding parameters are used to code a video stream and transmit the coded video stream via the wireless network, and receive a multimedia data via the wireless network. Next, the quality of the wireless network is detected. When the quality is poor, the video coding parameters are changed. Finally, the quality of received multimedia data is detected. When the quality of received multimedia data is poor, the video coding parameters are changed.

Abstract: In a method of automatically selecting audio format for output signal of a tuner, a SAW filter is configured to a bandwidth of 5.5 MHz for filtering IF signal so as to generate CVBS signal and SSIF signal. Then, band-pass filters are used to detect a back porch of the CVBS signal thereby determining whether signal amplitude at a center frequency of 4.43 MHz is greater than that at a center frequency of 3.58 MHz. Finally, a bandwidth of 4.5 MHz is assigned to the SAW filter for filtering the intermediate frequency signal to re-generate the CVBS signal when the amplitude at 4.43 MHz is smaller than that at 3.58 MHz. Further, a video decoder decodes the CVBS signal to determine a video format from NTSC, PAL-M, and PAL-N formats, and an audio decoder decodes the SSIF signal to determine an audio format from MN, BG, DK, and I formats.

Abstract: An optical disc identifying device includes an optical pickup head, a digital signal processor and a radio frequency amplifier. The optical pickup head has a plurality of laser diodes and a lens. During a start-up procedure, a non-blue laser diode of the optical pickup head is turned on to irradiate a loaded optical disc, thereby generating an electronic signal. The digital signal processor outputs a driving signal, thereby controlling a motor driver to move the lens in a focusing direction. The radio frequency amplifier receives the electronic signal during the movement of the lens, thereby generating a first signal. The digital signal processor includes a detecting unit for comparing the first signal with a slicing signal to generate a pulse signal, and determining whether the optical disc is a blue-ray disc or a non-blue-ray disc according to a pulse number of the pulse signal.

Abstract: Vertical sync signal separation apparatus and method are provided. The vertical sync signal separation apparatus includes a parameter detecting unit, a threshold generating unit and a vertical sync signal generating unit. The parameter detecting unit measures a composite sync signal to obtain a maximum and a second maximum positive pulse width, and a maximum and a second maximum negative pulse width. The threshold generating unit outputs a positive pulse threshold based on the maximum and second maximum positive pulse width, and outputs a negative pulse threshold based on the maximum and second maximum negative pulse width. The vertical sync signal generating unit outputs a vertical sync signal by comparing the composite sync signal against the positive pulse threshold and the negative pulse threshold. As such, this apparatus can correctly separate a vertical sync signal from composite sync signals with different standards, thus increasing its supportability.

Abstract: A progressive JPEG image decoding method is provided. In the decoding method, a non-zero history table and a sign table of each variable length decoding (VLD) result are recorded and used as a reference for decoding the next scan layer. The decoded coefficients are no longer directly stored in a memory so as to save the memory space. Accordingly, an image can be decoded and displayed correctly even with limited memory space.

Abstract: A method for detecting a typical defect area on a disc track includes the following steps. Firstly, a source signal is provided. Then, first and second signals are generated according to the source signal. The first and second signals are held at the peak level of the source signal and respectively decreased at first and second drop rates. Then, first and second threshold values are subtracted from the first and second signals to generate first and second slice signals, respectively. Afterwards, the source signal is compared with either the first slice signal or the second slice signal. When the first slice signal is larger than the source signal, a typical defect signal is changed from a first level to a second level. Whereas, the typical defect signal is changed from the second level to the first level when the second slice signal is smaller than the source signal.

Abstract: A highly linear variable-gain low noise amplifier is a cascode amplifier. The cascode amplifier includes a gain control circuit, a load circuit, a current steering circuit and an input circuit. The gain control circuit is used for receiving a gain adjusting voltage, thereby generating a resistance adjusting signal and a current steering control signal. The load circuit includes plural variable resistors. The resistances of the variable resistors are adjusted according to the resistance adjusting signal. The current steering circuit is connected to the load circuit through plural current paths for adjusting a current ratio between the plural current paths according to the current steering control signal. The current steering circuit has differential signal output terminals. The input circuit is connected to the current steering circuit. The input circuit has differential signal input terminals.

Abstract: A data recovery apparatus and method by using over-sampling are provided. The data recovery apparatus by using over-sampling includes an over-sampling module, a data regeneration unit, a phase alignment unit, a phase decision module, and an output data correction unit. The over-sampling module samples serial data according to a clock signal, so as to output M-bit data, in which each bit in the serial data is sampled N times. The phase alignment unit selects specific M-bit data from a P-bit signal output by the data regeneration unit, and distinguishes the specific M-bit data to X groups of N-bit signals. The phase decision module determines a direction of phase adjustment according to the specific M-bit data. The output data correction unit selects and outputs first or second recovery data constituted by first or second specific bits of each group of N-bit signal according to the direction of phase adjustment.

Abstract: A DTMB-based control system includes a carrier mode detector, a TPS decoder, a first latch, a second latch, and a latch controller. The carrier mode detector receives a number of NTPS and NCS of input signals to thereby produce an amplitude sign signal and a carrier sign signal for accordingly determining a carrier mode to be multi- or single-carrier mode. The TPS decoder receives the NTPS input signals and accordingly determines a codeword index signal. The first latch locks the amplitude sign signal and the carrier sign signal. The second latch locks the codeword index signal. The latch controller receives a frame number and drives the first latch to lock the amplitude sign signal and the carrier sign signal or drives the second latch to lock the codeword index signal.

Abstract: A timing controller for an LCD panel includes a signal receiver, a data reader, a signal receiver, a logic control unit, and a data conversion unit. The signal receiver receives transmitted signals, and the data reader acquires data from the signal receiver. The logic control unit receives the data acquired by the data reader to generate pixel data, and the data conversion unit receives the pixel data and converts them into serial signals. The timing controller converts the pixel data and the control commands into serial signals, and then they are transmitted in serial to each of the source driver chips.

Abstract: An image format conversion system includes a horizontal filter to receive an image input signal with a frequency of a first clock signal in order to perform a filtering operation to thereby produce a horizontal filtering image signal; a first FIFO to temporarily store the horizontal filtering image signal; a 2D image interpolator to perform a deinterlacing, a vertical interpolation and a horizontal interpolation operations on the horizontal filtering image signal to further produce a scaled progressive image signal; a second FIFO connected to the 2D image interpolator to temporarily store the scaled progressive image signal; an interpolation clock controller to receive a second clock signal and produce multiple enable signals in order to enable the horizontal filter and the 2D image interpolator, wherein the second clock signal has a frequency independent of the frequency of the first clock signal.

Abstract: An apparatus for data strobe and timing variation detection of an SDRAM interface includes a differential-signal to single-end signal converter, a first phase delay circuit, a data latch circuit. The differential-signal to single-end signal converter receives a differential data strobe signal from the SDRAM interface and converts the signal into a single-end data strobe signal. The first phase delay circuit is connected to the differential-signal to single-end signal converter to delay the phase of the single-end data strobe signal for producing a delayed data strobe signal. The data latch circuit is connected to the phase delay circuit to latch synchronous data from the SDRAM interface according to the delayed single-end data strobe signal.