Abstract: A flash module has raw-NAND flash memory chips accessed over a physical-block address (PBA) bus by a NVM controller. The NVM controller is on the flash module or on a system board for a solid-state disk (SSD). The NVM controller converts logical block addresses (LBA) to physical block addresses (PBA). Data striping and interleaving among multiple channels of the flash modules is controlled at a high level by a smart storage transaction manager, while further interleaving and remapping within a channel may be performed by the NVM controllers. A SDRAM buffer is used by a smart storage switch to cache host data before writing to flash memory. A Q-R pointer table stores quotients and remainders of division of the host address. The remainder points to a location of the host data in the SDRAM. A command queue stores Q, R for host commands.

Abstract: A swivel-type portable flash device includes a C-shaped swivel cover that rotates (swivels) relative to a housing between an open position in which a plug connector is exposed for insertion in a host system, and a closed position in which the plug connector is covered and protected by the swivel cover. The swivel cover is permanently rotatably connected to the housing by way of ring-shaped protrusions that are movably engaged inside corresponding recessed ring-shaped grooves formed in upper/lower walls of the housing, whereby the swivel cover is manually rotatable relative to the housing between the opened and closed positions. The swivel cover also includes locking structures (e.g., locking notches) disposed on the ring-shaped protrusions, and the housing includes second locking structures disposed in the recessed ring-shaped grooves, where the first locking structures operably engage the second locking structures to prevent rotation of the swivel cover when the plug connector is in the closed position.

Abstract: An extended universal serial bus (USB) storage device is described herein. According to one embodiment, an extended USB storage device includes a printed circuit board assembly (PCBA) having a flash memory device and a flash controller mounted thereon, and an extended USB connector plug coupled to the PCBA for providing a USB compatible interface between an external device and the flash memory device and the flash controller, wherein the extended USB connector plug includes a first end used to couple to the external device and a second end coupled to the flash memory device and the flash controller. The extended USB connector plug includes multiple communication interfaces. Other methods and apparatuses are also described.

Abstract: High endurance non-volatile memory devices (NVMD) are described. A high endurance NVMD includes an I/O interface, a NVM controller, a CPU along with a volatile memory subsystem and at least one non-volatile memory (NVM) module. The volatile memory cache subsystem is configured as a data cache subsystem. The at least one NVM module is configured as a data storage when the NVMD is adapted to a host computer system. The I/O interface is configured to receive incoming data from the host to the data cache subsystem and to send request data from the data cache subsystem to the host. The at least one NVM module may comprise at least first and second types of NVM. The first type comprises SLC flash memory while the second type MLC flash. The first type of NVM is configured as a buffer between the data cache subsystem and the second type of NVM.

Abstract: Various embodiments of a USB drive pen device are disclosed herein. In one embodiment, a USB drive pen device includes a USB plug assembly having a flash controller and a flash memory device, a pusher assembly including a rotator having one or more tabs disposed thereon, and a housing for housing at least a portion of the USB plug assembly and the pusher assembly. The housing includes a tunnel and an inner tube extended from the tunnel disposed within the housing. An intersection between the tunnel and inner tube includes one or more angled corners to lock the USB plug assembly in either a deployed position or a retracted position. Other methods and apparatuses are also described.

Abstract: Methods and systems of managing memory addresses in a large capacity multi-level cell based flash memory device are described. According to one aspect, a flash memory device comprises a processing unit to manage logical-to-physical address correlation using an indexing scheme. The flash memory is partitioned into N sets. Each set includes a plurality of entries (i.e., blocks). N sets of partial logical entry number to physical block number and associated page usage information (hereinafter ‘PLTPPUI’) are stored in the reserved area of the MLC based flash memory. Only one the N sets is loaded to address correlation and page usage memory (ACPUM), which is a limited size random access memory (RAM). In one embodiment, static RAM (SRAM) is implemented for fast access time for the address correlation. LSA received together with the data transfer request dictates which one of the N sets of PLTPPUI is loaded into ACPUM.

Abstract: A flash module has raw-NAND flash memory chips accessed over a physical-block address (PBA) bus by a NVM controller. The NVM controller is on the flash module or on a system board for a solid-state disk (SSD). The NVM controller converts logical block addresses (LBA) to physical block addresses (PBA). Data striping and interleaving among multiple channels of the flash modules is controlled at a high level by a smart storage transaction manager, while further interleaving and remapping within a channel may be performed by the NVM controllers. A SDRAM buffer is used by a smart storage switch to cache host data before writing to flash memory. A Q-R pointer table stores quotients and remainders of division of the host address. The remainder points to a location of the host data in the SDRAM. A command queue stores Q, R for host commands.

Abstract: High endurance non-volatile memory devices (NVMD) are described. A high endurance NVMD includes an I/O interface, a NVM controller, a CPU along with a volatile memory subsystem and at least one non-volatile memory (NVM) module. The volatile memory cache subsystem is configured as a data cache subsystem. The at least one NVM module is configured as a data storage when the NVMD is adapted to a host computer system. The I/O interface is configured to receive incoming data from the host to the data cache subsystem and to send request data from the data cache subsystem to the host. The at least one NVM module may comprise at least first and second types of NVM. The first type comprises SLC flash memory while the second type MLC flash. The first type of NVM is configured as a buffer between the data cache subsystem and the second type of NVM.

Abstract: A hybrid storage device comprises both solid-state disk (SDD) and at least one hard disk drive (HDD). The hybrid storage device has at least two operational modes: concatenation and safe. According to one aspect, the total capacity of hybrid storage device is the sum of SSD and at least one HDD in a concatenation or big mode, while the total capacity is the capacity of the HDD in a safe mode. In one embodiment, HDD is configured for storing a copy of the SSD's contents in a reserved area. In another, SSD comprises more than one identical flash memory devices controlled by a RAID controller.

Abstract: In an electronic data storage device accessed by a host computer motherboard, a fingerprint sensor scans a fingerprint of a user of the electronic data storage device and generates fingerprint scan data. A processing unit activates an input/output interface circuit to store a data file and fingerprint reference data obtained by scanning a fingerprint of a person authorized to access the data file in a memory device having non-volatile memory, where the processing unit transmits the data file to the host computer motherboard upon verifying that the user of the electronic data storage device is authorized to access the data file stored in the memory device as a result of comparison between the fingerprint scan data from the fingerprint sensor and the fingerprint reference data. Other methods and apparatuses are also described.

Abstract: Phase-change memory (PCM) cells store data using alloy resistors in high-resistance amorphous and low-resistance crystalline states. The time of the memory cell's set-current pulse can be 100 ns, much longer than read or reset times. The write time thus depends on the write data and is relatively long. A page-mode caching PCM device has a lookup table (LUT) that caches write data that is later written to an array of PCM banks. Host data is latched into a line FIFO and written into the LUT, reducing write delays to the relatively slow PCM. Host read data can be supplied by the LUT or fetched from the PCM banks. A multi-line page buffer between the PCM banks and LUT allows for larger block transfers using the LUT. Error-correction code (ECC) checking and generation is performed for data in the LUT, hiding ECC delays for data writes into the PCM banks.

Abstract: A RAM mapping table is restored from flash memory using plane, block, and page addresses generated by a physical sequential address counter. The RAM mapping table is restored following a plane-interleaved sequence generated by the physical sequential address counter using interleaved bits extracted from the lowest bits of the logical block index. These plane-interleave bits are split into a LSB and a MSB, with middle physical block bits between the LSB and MSB. The physical sequential address counter generates a physical block number by incrementing the plane-interleave bits before the middle physical block bits, and then relocating the MSB to above the middle physical block bits. This causes blocks to be accessed in a low-high sequence of 0, 1, 4096, 4097, 2, 3, 4098, 4099, etc. in the four planes of flash memory. Background recycling and ECC writes are also performed.

Abstract: Peripheral devices store data in non-volatile phase-change memory (PCM). PCM cells have alloy resistors with high-resistance amorphous states and low-resistance crystalline states. The peripheral device can be a Serial AT-Attachment (SATA) or integrated device electronics (IDE) PCM solid-state disk or a Multi-Media Card/Secure Digital (MMC/SD) card. A peripheral PCM controller accesses PCM mass storage devices containing PCM memory chips that form a mass-storage device that is block-addressable rather than randomly-addressable. SATA, IDE, or MMC/SD transactions from a host bus are read by a bus transceiver on the peripheral PCM controller. Various routines that execute on a CPU in the peripheral PCM controller are activated in response to commands in the host-bus transactions. A PCM controller in the peripheral controller transfers data from the bus transceiver to the PCM mass storage devices for storage.

Abstract: A hybrid storage device comprises both solid-state disk (SDD) and at least one hard disk drive (HDD). The hybrid storage device has at least two operational modes: concatenation and safe. According to one aspect, the total capacity of hybrid storage device is the sum of SSD and at least one HDD in a concatenation or big mode, while the total capacity is the capacity of the HDD in a safe mode.

Abstract: High endurance non-volatile memory devices (NVMD) are described. A high endurance NVMD includes an I/O interface, a NVM controller, a CPU along with a volatile memory subsystem and at least one non-volatile memory (NVM) module. The volatile memory cache subsystem is configured as a data cache subsystem. The at least one NVM module is configured as a data storage when the NVMD is adapted to a host computer system. The I/O interface is configured to receive incoming data from the host to the data cache subsystem and to send request data from the data cache subsystem to the host. The at least one NVM module may comprise at least first and second types of NVM. The first type comprises SLC flash memory while the second type MLC flash. The first type of NVM is configured as a buffer between the data cache subsystem and the second type of NVM.

Abstract: A press-push type computer peripheral “flash drive” device includes an elongated (e.g., metal) tubular casing containing a PCBA having a plug connector. A plastic housing assembly includes front and rear cap portions mounted over the open ends of the tubular casing, and a fixed plastic sleeve portion disposed in the tubular casing. The PCBA is secured to a plastic sliding rack structure that is disposed in the tubular casing and includes an actuating button protruding through a slot formed in a wall of the tubular casing. When the actuating button is manually pushed and slid along the slot, a portion of the sliding rack structure slides against the plastic sleeve portion in deploying and retracting the USB connector out of the device.

Abstract: A flash memory device includes one or two panels that are attached solely by a thermal bond adhesive to either a frame or integrated circuits (e.g., flash memory devices) disposed on a PCBA. The frame is disposed around the PCBA and supports peripheral edges of the panels. The thermal bond adhesive is either heat-activated or heat-cured, and is applied to either the memory devices, the frame or the panels, and then compressed between the panels and flash memory devices/frame using a fixture. The fixture is then passed through an oven to activate/cure the adhesive. An optional insulating layer is disposed between the panels and the ICs. An optional conforming coating layer is formed over the ICs for preventing oxidation of integrated circuit leads or soldering area, covering or protecting extreme temperature exposure either cold or hot, and waterproofing for certain military or industrial applications.

Abstract: A portable memory card including a molded plastic casing formed over a memory device and other circuits mounted on a substrate such that the molding material extends over side edges of the substrate to provide accurate width and thickness dimensions. Contact pads are formed on a lower surface of the PCBA substrate, which is exposed through a bottom of the casing. The PCBA is fabricated on a substrate carrier, then positioned inside of a mold assembly. During the molding process, a rod extends from an upper portion of the mold assembly and pushes the substrate against the lower surface. A vacuum is then applied to hold the substrate against the lower surface of the mold, and the rod is subsequently withdrawn from the mold cavity during injection of the molten molding material. A single cavity mold assembly provides molding material extends over front and back edges of the memory card.

Abstract: Systems and methods for communicating using various protocols through the Secured Digital (SD) physical interface are disclosed. The invention covers, among others, single-mode and multi-mode hosts, single-mode and multi-mode devices, as well as techniques for initializing these hosts and devices in order to facilitate the aforementioned communication.