Abstract: A method is provided for inserting a path instruction during compilation of computer programs for a processor having multiple functional resources. A path instruction is inserted in the order of object code instruction during the reordering of the instructions in response to a simulation of the run-time environment of the target machine to direct that the path of execution for a subsequent object code instruction be in accordance with an optimum path of execution for the object code instruction as determined by the simulation is different than a preselected default path of execution for an object code instruction for a similar type of object code operation.

Abstract: A method and apparatus for manufacturing large area multilayer interconnects for electronic substrates and circuit boards uses high density area array interconnections that are created by solid state diffusion. Two or more pretested subsections are electrically and mechanically joined together to simultaneously form a multilayer substrate without employing a flow-type connection where the conductive interconnect material is entirely in a liquid phase at some point during the joining process. Each substrate is comprised of a planar dielectric substrate having a plurality of conductive layers. On at least one surface of the substrate a conductive pad lay is formed having a plurality of interconnect pads. The interconnect pads are positioned at a uniform height above the surface of the dielectric substrate and include a base metal layer, a top metal layer with at least one of the conductive pad layers have a donor metal disposed on top of the top metal layer.

Abstract: Methods and apparatus for a maintenance and control system for sensing and controlling the numerous sections of a highly parallel multiprocessor system. The control and maintenance system communicates with all processors, all peripheral systems, all user interfaces to the multiprocessor system, a system console, and the power and environmental control subsystems.

Abstract: The present invention includes methods and apparatus for creating a packaging architecture for a highly parallel multiprocessor system. The packaging architecture of the present invention can provide for distribution of power, cooling and interconnections at all levels of components in a highly parallel multiprocessor system, while maximizing the number of circuits per unit time within certain operational constraints of such a multiprocessor system.

Abstract: A signaling mechanism for sending and receiving signals to and from any one of all of a plurality of devices, including peripheral controllers and processors, in a multiprocessor system. The signaling mechanism includes two switches, a first switch routing a signal command generated by the device to a signal dispatch logic and a second switch for receiving signals generated by the signal dispatch logic and routing the signals to the selected device. The signal dispatch logic receiving the signal command, decodes the destination select value and generates a signal to be sent to the selected device. The signal command includes a destination select value representing a device selectably determined by the device. The signaling mechanism also includes an arbitration mechanism connected to the signal dispatch logic and the first switch for resolving simultaneous conflicting signal commands issued by two or more devices.

Abstract: Communication among processors having differing operating speeds by providing wake queues in which slower processors can queue entries, access to which by multiple concurrent producers and multiple concurrent consumers is synchronized or controlled using global registers. When a faster processor executes a kernel process for handling a wake queue, an entry is fetched from the wake queue and information stored in the entry is used to process the entry.

Abstract: A method for scheduling instructions for a processor having multiple functional resources wherein the reordering of the instructions is accomplished in response to a simulation of the run-time environment of the target machine. The simulation of the run-time environment of the target machine is performed at compile time after the machine instructions have been generated by a compiler, or after instruction generation by an assembler. The present invention rearranges the machine instructions for a basic block of instructions into an order that will result in the fastest execution based upon the results of the simulation of the interaction of the multiple functional resources in the target machine.

Abstract: A cluster architecture for a highly parallel multiprocessor computer processing system is comprised of one or more clusters of tightly-coupled, high-speed processors capable of both vector and scalar parallel processing that can symmetrically access shared resources associated with the cluster, as well as the shared resources associated with other clusters.

Abstract: A parser for parsing computer programs in a compiler has parsing tables arranged as linear vectors. In a reduction portion of the parser, a production table and a lookahead set table have paired entries at identical address offsets such that a one-to-one relationship exists between each lookahead set in the lookahead set table and the representation of the lookahead set in the lookahead set table. In a read transition portion of the parser, an entrance symbol table has entries paired with transition state representations and each pair being at an identical address offset in the respective tables. For a reduction or read transition operation, the lookahead set table or the entrance symbol table is scanned to find the appropriate entry. Once the appropriate entry is found, the production table or the transition state table is addressed using the offset of the appropriate entry found during the scanning process.

Abstract: A fast interrupt mechanism is capable of simultaneously interrupting a community of associated processors in a multiprocessor system. The fast interrupt mechanism enables the more effective debugging of software executing on a multiprocessor system by allowing all of the processors in a community associated with a parallel process to be halted within a limited number of clock cycles following a hardware exception or processor breakpoint. The fast interrupt mechanism consists of a set of registers that are used to identify associations among multiple processors, a comparison matrix that is used to select processors to be interrupted, a network of interconnections that transmit interrupt events to and from the processors, and elements in the processors that create and respond to fast interrupt events.

Abstract: The graphical display of compiler intermediate database representation is produced to function as an aid in the development of highly optimizing compilers, the inspection of the compiler-generated intermediate representation, and the analysis of the effects of a highly optimizing compiler upon original source code. This method extracts the intermediate representation and transforms it into simultaneous displays of the program statements, expressions, basic blocks, machine instructions, and original source code for a particular source position, statement, expression, basic block, or machine instruction.

Abstract: An integrated software architecture for a highly parallel multiprocessor system having multiple tightly-coupled processors that share a common memory efficiently controls the interface with and execution of programs on such a multiprocessor system. The software architecture combines a symmetrically integrated multithreaded operating system and an integrated parallel user environment. The operating system distributively implements an anarchy-based scheduling model for the scheduling of processes and resources by allowing each processor to access a single image of the operating system stored in the common memory that operates on a common set of operating system shared resources. The user environment provides a common visual representation for a plurality of program development tools that provide compilation, execution and debugging capabilities for multithreaded user programs and assumes parallelism as the standard mode of operation.

Abstract: A modular compilation system that utilizes a fully integrated hierarchical representation as a common intermediate representation to compile source code programs written in one or more procedural programming languages into an executable object code file. The structure of the integrated common intermediate representation supports machine-independent optimizations, as well as machine-dependent optimizations, and also supports source-level debugging of the executable object code file. The integrated hierarchical representation (IHR) is language independent and is shared by all of the components of the software development system, including the debugger.

Abstract: A special purpose arithmetic boolean unit is capable of performing extremely parallel bit-level boolean operations, particularly bit matrix manipulations. The special purpose arithmetic boolean unit is especially adapted for use in traditional vector processors, thereby enabling a vector processor to effectively solve extremely parallel MIMD or SIMD boolean problems without requiring an array processor or massively parallel supercomputer.

Abstract: A distributed architecture for the input/output system for a multiprocessor system provides for equal and democratic access to all shared hardware resources by both the processors and the external interface ports of the multiprocessor system. This allows one or more input/output concentrators attached to the external interface ports to have complete access to all of the shared hardware resources across the multiprocessor system without requiring processor intervention. The distributed input/output system provides for communication of data and control information between a set of common shared hardware resources and a set of external data sources. The result is a highly parallel multiprocessor system that has multiple parallel high performance input/output ports capable of operating in a distributed fashion.

Abstract: A multiple request toggling (MRT) arbitration system for prioritizing requests to a set of shared resources by multiple requestors, especially requests by multiple processors to shared resources in a multiprocessor system. The MRT arbitration system assigns priority to multiple requests on a first-come, first-serve basis with the priority of multiple simultaneous requests being resolved through an arbitration network.

Abstract: Global registers for a multiprocessor system support multiple parallel access paths for simultaneous operations on separate sets of global registers, each set of global registers referred to as a global register file. An arbitration mechanism associated with the global registers is used for resolving multiple, simultaneous requests to a single global register file. An arithmetic and logical unit (ALU) is also associated with each global register file for allowing atomic arithmetic operations to be performed on the entire register value for any of the global registers in that global register file.

Abstract: The present invention provides a parallel memory scheduler for execution on a high speed highly parallel multiprocessor architecture. The operating system software provides intelligence and efficiency in swapping out process images to facilitate swapping in another process. The splitting and coalescing of data segments are used to fit segments in to current free memory even though a single contiguous space of sufficient size does not exist. Mapping these splits through data control register sets retains the user's contiguous view of the address space. The existence of dual images and partial swapping allows efficient, high speed swapping. Candidates for swap out are chosen in an intelligent fashion, selecting only those candidates which will most efficiently aLlow the swapin of another process.

Abstract: A structure for an electrical cable which may be used as a high-frequency signal transmission line and which includes a jacket which is highly permeable by fluids to reduce the time required for stabilization of impedance and transmission speed of the cable upon placement into an environment characterized by a fluid dielectric having a different dielectric constant. The permeable jacket also facilitates electrical connection to a shield conductor of the transmission line, exposed through apertures in the jacket, by use of electrically conductive potting materials, and without the need to remove any portions of the jacket surrounding the shield conductor to which electrical connection is to be made.

Abstract: A method for representing scalar data dependencies for an optimizing compiler wherein a global scalar data dependence graph is created to represent all of the scalar objects in an entire program. The scalar data dependencies are represented as three chains: a use-definition chain (ud); a definition-use chain (du) or a definition-definition chain (dd), and is created for the entire program and is maintained during the entire compilation or assembly of the program. The method for determining scalar data dependences for the entire program starts by analyzing the scalar data dependences within each basic block, in a single pass, processes all definitions and uses of all non-array data objects in the basic block, including simple variables and complex data objects such as records, unions, pointers and procedure calls in the presence of aliasing.