Patents Assigned to SUPERCOMPUTING SYSTEMS AG
  • Patent number: 10691080
    Abstract: According to an aspect of the invention, a computerised system, in particular control system is provided, which is configured, from an input vector (In) which represents a discrete number of input variables and from a state vector (Zn) which represents a discrete number of state variables, to determine a new state vector (Zn+1) whose state variables are updated, as well as an output vector (On) which represents a discrete number of output variables, wherein the output variables are provided for controlling at least one appliance and/or for outputting information. The system comprises a plurality of computation units which in parallel determine the new state vector and the output vector from the input vector and the state vector. According to the invention, the system is configured such that at least all news state vectors are exchanged between the computation units after each cycle.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: June 23, 2020
    Assignee: Supercomputing Systems AG
    Inventors: Anton Gunzinger, Martin Dorigatti, David Beyeler, Philipp Stadelmann, Richard Huber
  • Patent number: 9783215
    Abstract: According to one aspect of the invention, the circuit logic of an existing relay interlocking system is mapped onto a functionally equivalent circuit of electronic components. Semiconductor components that are functionally identical to the components of the relay circuit are thus preferably used. The circuit logic is created, for example, by transforming an interlocking table or track diagram into a logic circuit by means of an automatic compiler according to predefined rules.
    Type: Grant
    Filed: June 22, 2010
    Date of Patent: October 10, 2017
    Assignee: SUPERCOMPUTING SYSTEMS AG
    Inventors: Anton Gunzinger, Markus Montigel, David Mueller, Markus Herrli
  • Publication number: 20090177832
    Abstract: The invention relates to multi-computer systems, wherein each computer (100, 200, . . . , N00) comprises a central processor (101, 201, . . . , N01) and working memory (103, 203, . . . , N03). According to one aspect of the invention, the “Internal High Speed Interconnect” (104, 204, . . . , N04) is extended beyond the internal limits of the computer and impinges upon the “High Speed Switch” (1). If need be, a single data conversion is performed in the High Speed Switch (100, 200, . . . , N00), specifically at the High Speed Interconnect Interface, and from that point the data is transferred through the “Switching Matrix” in a manner analogous to the state of the art.
    Type: Application
    Filed: November 10, 2008
    Publication date: July 9, 2009
    Applicant: SUPERCOMPUTING SYSTEMS AG
    Inventors: Anton Gunzinger, Tobias Gysi, Markus Herrli, Leonardo Leone, Stephan Moser, David Mueller
  • Patent number: 7263630
    Abstract: An error tolerant computer controlled system comprises several computers working redundantly and controlling actuators based on signals from sensors and input devices. Each data item emitted by each computer is simultaneously sent through differing communication paths to each actuator, such that in normal operation each actuator receives each data item through several paths. This system continues to function properly even in case of a failure without requiring any re-routing of the data items, which makes it easier to design, analyze and test and thereby increases its reliability.
    Type: Grant
    Filed: January 23, 2004
    Date of Patent: August 28, 2007
    Assignee: Supercomputing System AG
    Inventor: Thomas Michael Sailer
  • Publication number: 20040195460
    Abstract: An error tolerant computer controlled system comprises several computers working redundantly and controlling actuators based on signals from sensors and input devices. Each data item emitted by each computer is simultaneously sent through differing communication paths to each actuator, such that in normal operation each actuator receives each data item through several paths. This system continues to function properly even in case of a failure without requiring any re-routing of the data items, which makes it easier to design, analyze and test and thereby increases its reliability.
    Type: Application
    Filed: January 23, 2004
    Publication date: October 7, 2004
    Applicant: Supercomputing System AG
    Inventor: Thomas Michael Sailer