Abstract: A data optimization engine for deoptimizing selected frames of a first stream of data, comprising a receive interface circuit coupled to an optimization processor. The receive interface circuit is configured for receiving the first stream of data. The receive interface circuit includes a traffic controller circuit for separating frames in the first stream of data into a first deoptimizable frame and a first non-deoptimizable frame, and a deoptimization front-end circuit coupled to the traffic controller circuit to receive at least a first portion of the first deoptimizable frame.

Abstract: A data optimization engine for optimizing selected frames of a first stream of data. The data optimization engine includes a transmit interface circuit coupled to an optimization processor, the transmit interface circuit being configured for receiving the first stream of data. The transmit interface circuit includes a traffic controller circuit for separating frames in the first stream of data into a first optimizable frame and a first non-optimizable frame, and an optimization front-end circuit coupled to the traffic controller circuit to receive at least a first portion of the first optimizable frame. The optimization front-end circuit includes a protocol conversion circuit configured to convert data in the first portion of the first optimizable frame from a first protocol to a second protocol suitable for processing by the optimization processor, the first protocol specifies a first word length, the second protocol specifies a second word length different from the first word length.

Abstract: A data optimization engine disposed inline with a first communication channel and a second communication channel. The data optimization engine comprises a transmit interface circuit configured to receive a first data stream from the first communication channel and to obtain a first data file from the first data stream. The data optimization engine further includes an optimization processor coupled to the transmit interface circuit for receiving a second data file from the transmit interface circuit. The second data file represents the first data file after the first data file has been processed by the transmit interface circuit into a format suitable for optimization by the optimization processor. The optimization processor performs one of a compression and an encryption on the second data file, thereby obtaining all optimized data file. In one embodiment, the first data file is a Fiber Channel data frame.