Patents Assigned to SuperH, Inc.
  • Semiconductor memory device and semiconductor integrated circuit device
    Patent number: 7385870
    Abstract: A leakage current of the MOS transistor of a power control section at a standby time is drastically reduced and the reduction of the consumption power is achieved. A memory module is provided with power control sections. When either of the memory mats is not selected, the power control sections stop the power supply voltage to a non-selected memory mat, a word driver, an input-output circuit, a control circuit and an output circuit. At the standby time of the memory module, the power control section stops a power supply to power control sections, a control circuit, a predecoder circuit, and an input circuit. In this manner, the leakage current of the MOS transistor of the power control sections at the standby time can be drastically reduced.
    Type: Grant
    Filed: June 20, 2007
    Date of Patent: June 10, 2008
    Assignees: Renesas Technology Corp., SuperH, Inc., Renesas Northern Japan Semiconductor, Inc., Hitachi ULSI Systems Co., Ltd.
    Inventors: Noriyoshi Watanabe, Noriaki Maeda, Masanao Yamaoka, Yoshihiro Shinozaki
  • Semiconductor memory device and semiconductor integrated circuit device
    Patent number: 7251182
    Abstract: A leakage current of the MOS transistor of a power control section at a standby time is drastically reduced and the reduction of the consumption power is achieved. A memory module is provided with power control sections. When either of the memory mats is not selected, the power control sections stop the power supply voltage to a non-selected memory mat, a word driver, an input-output circuit, a control circuit and an output circuit. At the standby time of the memory module, the power control section stops a power supply to power control sections, a control circuit, a predecoder circuit, and an input circuit. In this manner, the leakage current of the MOS transistor of the power control sections at the standby time can be drastically reduced.
    Type: Grant
    Filed: February 15, 2006
    Date of Patent: July 31, 2007
    Assignees: Renesas Technology Corp., SuperH, Inc., Renesas Northern Japan Semiconductor, Inc., Hitachi ULSI Systems Co., Ltd.
    Inventors: Noriyoshi Watanabe, Noriaki Maeda, Masanao Yamaoka, Yoshihiro Shinozaki
  • Semiconductor memory device and semiconductor integrated circuit device
    Patent number: 7031220
    Abstract: A leakage current of the MOS transistor of a power control section at a standby time is drastically reduced and the reduction of the consumption power is achieved. A memory module is provided with power control sections. When either of the memory mats is not selected, the power control sections stop the power supply voltage to a non-selected memory mat, a word driver, an input-output circuit, a control circuit and an output circuit. At the standby time of the memory module, the power control section stops a power supply to power control sections, a control circuit, a predecoder circuit, and an input circuit. In this manner, the leakage current of the MOS transistor of the power control sections at the standby time can be drastically reduced.
    Type: Grant
    Filed: August 27, 2004
    Date of Patent: April 18, 2006
    Assignees: Renesas Technology Corp, SuperH, Inc., Renesas Northern Japan Semiconductor, Inc., Hitachi ULSI Systems Co., Ltd.
    Inventors: Noriyoshi Watanabe, Noriaki Maeda, Masanao Yamaoka, Yoshihiro Shinozaki