Abstract: Employed within an LED driver operating from the AC power line, the invention controls both input current and output power. With this regulation circuit, input current appears purely resistive, precisely tracking the input voltage waveshape. At the same time, it provides good line regulation and inherent phase dimmer compatibility, requiring no special circuitry to detect and handle a dimmer.

Abstract: This invention relates to medical ultrasonic imaging systems and, in particular, phased array imaging systems operating in different scan formats and imaging modalities. More specifically, the invention relates to the front-end processing of ultrasonic echoes.

Abstract: An improved power converter is disclosed.

Abstract: A method and system for extending the power output range of a power converter used for a lighting system is disclosed.

Abstract: An impedance matching transmission circuit for a transducer has a transmission medium connected to the transducer. A transmitting circuit is connected to the transmission medium with the transmitting circuit terminating in a reference circuit element. The transmitting circuit comprises an analog to digital converter having an analog input connected to the reference circuit element, and having a digital output. A digital to analog converter receives the digital output and generates an analog output signal in response thereto. A driver circuit is connected to the transmission medium and receives the analog output signal and supplies a driver signal to the transmission medium.

Abstract: The invention relates to auxiliary power supplies.

Abstract: A circuit for flicker suppression in a Light Emitting Diode (LED) has a latch. The latch has a first state set with a trailing edge of Pulse Width Modulated Dimming (PWMD) pulse, and a second state set delayed with respect to the PWMD trailing edge. A trigger circuit is coupled to the latch. The trigger circuit sends a signal to the latch to change to the second state when a decision point occurs during a time following a duty limit Dmax of a gate of a LED driver circuit.

Abstract: A Light Emitting Diode (LED) driver circuit for driving an LED string has a switch-mode power supply coupled to the LED string. A control circuit is provided and has a first terminal coupled to a pulse width modulated input and a second terminal coupled to the switch mode power supply. A disconnect switch is coupled to a third terminal of the control circuit and the LED string.

Abstract: An LED driver circuit for controlling direct current supplied to a plurality of serially connected segments of Light Emitting Diodes (LEDs) is disclosed. In one embodiment, the LED driver circuit comprises a self-commutating circuit, which comprises a plurality of current control elements, each current control element having two ends, a first end connected to a different end of each segment along the plurality of serially connected segments of LEDs and a second end connected to a path to ground. The path to ground comprises a sense resistor and the path to ground is shared by the second end of each current control element. Each current control element is coupled to an adjacent current control element by a cross-regulation circuit and controlled by a signal from an adjacent current control element.

Abstract: An integrated single channel or multi-channel ultrasound transmitter that minimizes the number of input connections to a controller such as an FPGA, field programmable gate array, or a custom integrated circuit in an ultrasound system. The method is accomplished by integrating, in low voltage logic, a means to store and or program the patterns required for the transmitter output. The number of logic input connections can be further reduced by further integrating, in low voltage logic, programmable individual time delays and frequency divider for each transmitter output.

Abstract: This document describes a new op-amp sharing technique for pipeline ADC without memory effect. The key features of this technique are: the usage of negative impedance converter and scaled replica of the op-amp input device to achieve zero error voltage, which in turns achieve low power dissipation due to the removal of the tradeoff between op-amp sharing and memory effect. With this technique much lower operation of pipeline ADC can be achieved for applications of data communications and image signal processing.

Abstract: An LED driver circuit is disclosed. The top of a string of series connected LED segments is connected to the output of a rectifier, which in turn is connected to an AC source. The string is tapped at various locations, including the bottom of the string. Each segment can consists of any number of serial or parallel connected LEDs. Current control elements or regulators sink current at each tap and are sequentially turned on and off one at a time, tracking the rectified sine wave voltage. Voltage across each regulator and current when conducting is individually controllable. The regulators may control current in a multitude of ways, including a constant current, or a current dependent on voltage across the regulators including a resistor, or a combination. The driver is self-commutating, with the sequencing of the current control elements an inherent feature closely integrated with the current control elements and providing optimal performance over variable operating conditions.

Abstract: An electrical waveform generating circuit has a programmable current source-driver. A digital switched current source is coupled to the programmable current source-driver and controlled by waveforms stored in the programmable current source-driver. A plurality of MOSFETs is coupled to the programmable current source driver. A first coupled inductor is connected to the plurality of high voltage MOSFETs. A transducer is coupled to the first coupled inductor.

Abstract: A phase shift generation circuit has an edge detector for generating first and second edge signals indicating first and second edges of an input pulse signal. The circuit comprises a divide by N circuit that divides the frequency of a first clock signal by N. The circuit comprises a pulse counter, which receives the first edge signal and the second clock signal, and outputs a group of signals representing the number of the second clock pulses between occurrences of the first edge signal. The circuit has a first recycling timer that outputs a group of pulses as a uniformly spaced group across the period of the input pulse. The circuit also has a second recycling timer that outputs a group of pulses as a uniformly spaced group across the period of the input pulse. The first and second recycling timers are used to generate a phase shifted output pulse.

Abstract: An adjustable shunt regulator circuit has two current paths in parallel, with each current path having a bipolar transistor therein with the bases of the bipolar transistors of the two current paths connected in common. One of the current paths has a high impedance node. A MOS transistor has a gate connected to the high impedance node, and a source and a drain. A resistor divide circuit is connected in parallel to the source and drain of the MOS transistor and provides the output of the regulator circuit. The resistor divide circuit has a first resistor connected in series with a second resistor at a first node. A feedback connects the first node to the bases of the bipolar transistors connected in common of the two current paths.

Abstract: A method of controlling an output current of a power supply circuit comprising a first converter stage for receiving an input voltage, a second converter stage delivering a regulated output current, a controlled switch for conducting the input current and the output current, the method comprising: detecting a portion of the input current conducted by the controlled switch; detecting a current in the controlled switch; deriving a difference between the current in the controlled switch and the portion of the input current conducted by the controlled switch; and maintaining the difference at a reference level.

Abstract: A 5 Ringer Equivalent Number (REN) ringer circuit has a wave generator. A flip-flop is coupled to the wave generator and has a non-inverting and an inverting output. A high voltage level translator is coupled to each of the non-inverting and the inverting outputs of the flip-flop. A source follower buffer is coupled to an output of each of the high voltage level translators.

Abstract: A phase shift generation circuit has an edge detector, which outputs a first and a second edge signal. The circuit also has a divide by N circuit, which receives a first clock signal and a group of signals representing a number N, and outputs a second clock signal. The circuit further comprises a pulse counter, which receives the first edge signal and the second clock signal, and outputs a group of signals representing the number of the second clock pulses between occurrences of the first edge signal. The circuit has first and second recycling timers, which output a group of pulses approximating a uniformly spaced group across the time duration of the period of the input pulse. The circuit also comprises at least one flip flop which generates a phase shifted output pulse.

Abstract: A multi-level high-voltage pulse generator integrated circuit has a digital logic-level control interface circuit. A pair of complementary MOSFETs is controlled by the digital control interface circuit. A pair of supply voltage rails is provided, wherein one of the pair of supply voltage rails is connected to each of the pair of complementary MOSFETs. A pair of Zener diodes is provided, wherein one of the pair of Zener diodes is connected to each of the pair of complementary MOSFETs. A pair of resistors is provided, wherein one of the pair of resistors is connected in parallel with each of the pair of Zener diodes. A pair of complementary voltage blocking-MOSFETs having predetermined gate bias voltages is provided, wherein each of the pair complementary voltage blocking-MOSFETs is attached to a corresponding one pair of complementary MOSFETs.

Abstract: An adjustable shunt regulator circuit has two current paths in parallel, with each current path having a bipolar transistor therein with the bases of the bipolar transistors of the two current paths connected in common. One of the current paths has a high impedance node. A MOS transistor has a gate connected to the high impedance node, and a source and a drain. A resistor divide circuit is connected in parallel to the source and drain of the MOS transistor and provides the output of the regulator circuit. The resistor divide circuit has a first resistor connected in series with a second resistor at a first node. A feedback connects the first node to the bases of the bipolar transistors connected in common of the two current paths.