Patents Assigned to Suzhou Qing Xin Fang Electronics Technology Co., Ltd.
  • Patent number: 11973029
    Abstract: Techniques for providing vertical integrations of semiconductor chips, magnetic chips, and lead frames. The techniques can include fabricating an integrated circuit (IC) device as a multi-layer IC structure that includes, within a sealed protective enclosure, a first layer including at least one magnetic chip, a second layer including at least one semiconductor chip or die, and a lead frame. The techniques can further include vertically bonding the magnetic chip in the first layer onto the topside of the lead frame, and vertically bonding the semiconductor chip or die in the second layer on top of the magnetic chip to form a multi-layer IC structure.
    Type: Grant
    Filed: February 9, 2022
    Date of Patent: April 30, 2024
    Assignee: SUZHOU QING XIN FANG ELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Jerry Zhijun Zhai
  • Patent number: 11532430
    Abstract: A laminated transformer-type transmitter-receiver device for transmitting or delivering electrical signals and/or power. The laminated device can include two metal shielding layers disposed between transmit and receive windings, which, in turn, are disposed between two magnetic layers. The laminated device further includes a dielectric isolation layer disposed between the two metal shielding layers. In the laminated device, no (or very little) common mode capacitance is distributed within the dielectric isolation layer, and no (or very little) common mode or “leakage” current flows across the dielectric isolation layer. As a result, various adverse effects of the common mode capacitance and the leakage current during operation of the laminated device are avoided.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: December 20, 2022
    Assignee: SUZHOU QING XIN FANG ELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Jerry Zhijun Zhai
  • Patent number: 11315873
    Abstract: Techniques for providing vertical integrations of semiconductor chips, magnetic chips, and lead frames. The techniques can include fabricating an integrated circuit (IC) device as a multi-layer IC structure that includes, within a sealed protective enclosure, a first layer including at least one magnetic chip, a second layer including at least one semiconductor chip or die, and a lead frame. The techniques can further include vertically bonding the magnetic chip in the first layer onto the topside of the lead frame, and vertically bonding the semiconductor chip or die in the second layer on top of the magnetic chip to form a multi-layer IC structure.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: April 26, 2022
    Assignee: SUZHOU QING XIN FANG ELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Jerry Zhijun Zhai
  • Patent number: 9871004
    Abstract: Semiconductor chip laminates and inductive, capacitive, and electromagnetic shielding laminate structures that can be integrated together to form electronic circuits for use in systems and devices such as smartphones, tablet computers, notebook computers, wearable electronic devices, portable medical devices, servers, networking equipment, industrial equipment, etc. Fabrications of such integrated laminate structures can be modularized into four (4) types of laminates, namely, inductive laminates, capacitive laminates, electromagnetic shielding laminates, and semiconductor chip laminates, which can be vertically laminated together and/or integrated side-by-side with high density to produce the desired electronic circuits, systems, and devices.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: January 16, 2018
    Assignee: Suzhou Qing Xin Fang Electronics Technology Co., Ltd.
    Inventor: Jerry Zhijun Zhai