Patents Assigned to SUZHOU WATECH ELECTRONICS CO., LTD.
  • Publication number: 20260088765
    Abstract: A radio frequency power amplifier device includes an active device, a grounded capacitor device, and an inductor assembly disposed on the grounded capacitor device. The inductor assembly is connected between the active device and the grounded capacitor device. The radio frequency power amplifier device and manufacturing method thereof of the embodiment of the present disclosure connect the inductor assembly between the active device and the grounded capacitor device, which is capable of improving the electromagnetic coupling problem due to the two bonding wires existing the parallel components in the conventional solution, so as to reduce the loss of the output signals, and improve the power amplifier efficiency.
    Type: Application
    Filed: September 19, 2025
    Publication date: March 26, 2026
    Applicant: SUZHOU WATECH ELECTRONICS CO., LTD.
    Inventor: Mengsu YANG
  • Publication number: 20250364950
    Abstract: Disclosed are an output network of a Doherty amplifier, a Doherty amplifier including the output network, and a design method of the Doherty amplifier. The output network of a Doherty amplifier including a main amplifier and an auxiliary amplifier, and the output network includes a combination node; a main output network connected between an output port of the main amplifier and the combination node; an auxiliary output network connected between an output port of the auxiliary amplifier and the combination node; and a merging matching network connected between the combination node and a radio frequency output port of the Doherty amplifier; the merging matching network is configured for the node impedance at the combination node being a complex impedance, and the main output network and the auxiliary output network are configured for the node impedance being matching with the goal load impedances of the main amplifier and the auxiliary amplifier.
    Type: Application
    Filed: November 1, 2022
    Publication date: November 27, 2025
    Applicant: SUZHOU WATECH ELECTRONICS CO., LTD.
    Inventors: Haoyu LIU, Shuangshuang ZHENG, Liang LIN
  • Publication number: 20250318227
    Abstract: A semiconductor structure includes a gate structure region; a source region and a drain region disposed on two sides of the gate structure respectively. The gate structure region includes a channel region and a gate region disposed from inside to outside. The channel region is surrounded inside an inner cavity of the gate region and attached to the source region, the drain region, and the gate region, and an ion doping type of the drain region, an ion doping type of the source region and an ion doping type of the channel region are same.
    Type: Application
    Filed: April 2, 2025
    Publication date: October 9, 2025
    Applicant: SUZHOU WATECH ELECTRONICS CO., LTD.
    Inventors: Dancheng YUE, Yaohui ZHANG, Yu LIU, Changchang WANG, Xiaoyu ZHANG
  • Publication number: 20250241016
    Abstract: Disclosed are a vertical coupling capacitance gate-controlled junction field effect transistor and a manufacturing method thereof. The vertical coupling capacitance gate-controlled junction field effect transistor includes a base of a first doping type; two bottom gates of the second doping type, formed inside the base and spaced apart in the lateral direction; a top gate of the second doping type, formed inside the base, where the top gate is located above the interval between the two bottom gates, and an interval is formed between the top gate and the bottom gate; a dielectric layer, formed on the base and located on the top gate; and a coupling capacitance upper electrode, formed on the dielectric layer; where the top gate is indirectly controlled by the coupling capacitance upper electrode spaced with the dielectric layer.
    Type: Application
    Filed: August 16, 2024
    Publication date: July 24, 2025
    Applicant: SUZHOU WATECH ELECTRONICS CO., LTD.
    Inventors: Xiaoyu ZHANG, Changchang WANG, Dancheng YUE
  • Publication number: 20250241017
    Abstract: Disclosed are a vertical trench coupling capacitance gate-controlled junction field effect transistor and a manufacturing method thereof. The vertical trench coupling capacitance gate-controlled junction field effect transistor includes a substrate of a first doping type, an epitaxial layer of the first doping type, and a plurality of repeating units disposed adjacently; where the epitaxial layer is disposed on the substrate, the substrate is served as a drain region, and each of the repeating units includes: two source regions of the first doping type; a trench; a gate of the second doping type; a dielectric; and a coupling capacitance upper electrode, where the gate is indirectly controlled by the coupling capacitance upper electrode spaced with the dielectric layer.
    Type: Application
    Filed: September 16, 2024
    Publication date: July 24, 2025
    Applicant: SUZHOU WATECH ELECTRONICS CO., LTD.
    Inventors: Xiaoyu ZHANG, Dancheng YUE, Changchang WANG
  • Publication number: 20250234571
    Abstract: An IGBT device includes a drift region of a first doping type; a plurality of pillar regions of the second doping type, disposed at intervals in the lateral direction within the drift region; and a transition layer of the first doping type, connected under the pillar region. The thickness of the transition layer is larger than 2 microns and less than or equal to 11 microns, and the doping concentration of the transition layer ranges from larger than or equal to 2.4×1014/cm3 to less than or equal to 2.4×1016/cm3, in order to solve the technical problem of a large turn-off energy loss due to the tail current of the conventional SJ-IGBT device in the turn-off stage.
    Type: Application
    Filed: July 16, 2024
    Publication date: July 17, 2025
    Applicant: SUZHOU WATECH ELECTRONICS CO., LTD.
    Inventors: Jinwei QI, Jinlong LAN
  • Publication number: 20250220939
    Abstract: A bipolar junction field effect transistor includes a drift region of a first doping type, formed in a cell area and a termination area of the bipolar junction field effect transistor; a plurality of pillar regions of a second doping type, extended in a vertical direction, spaced out in a lateral direction, and arranged in a drift region of a first doping type; a first doping type region and a well region of the second doping type formed inversely, successively arranged on the top of the pillar region in the cell area from near to far; and in the termination area, a field oxide layer provided above the drift region of the first doping type, where the pillar region in the termination area is in contact with the field oxide layer.
    Type: Application
    Filed: August 16, 2024
    Publication date: July 3, 2025
    Applicant: SUZHOU WATECH ELECTRONICS CO., LTD.
    Inventors: Jinwei QI, Qian LIU, Jinlong LAN
  • Publication number: 20250219597
    Abstract: Disclosed are a radio frequency power amplifier and a wireless signal transmitting system. The radio frequency power amplifier includes a first amplifying branch, comprising a first transistor and a first output circuit; and a second amplifying branch, comprising a second transistor and a second output circuit. The first output circuit comprises a line with an electrical length of 50 degrees to 90 degrees formed based on capacitors and inductors, and the second output circuit comprises a line with an electrical length of 120 degrees to 180 degrees formed based on capacitors and inductors.
    Type: Application
    Filed: July 9, 2024
    Publication date: July 3, 2025
    Applicant: SUZHOU WATECH ELECTRONICS CO., LTD.
    Inventor: Mengsu YANG
  • Publication number: 20250141405
    Abstract: Disclosed are an output network of a Doherty amplifier, a Doherty amplifier including the output network, and a design method of the Doherty amplifier. The output network includes a combination node, a main output network connected between an output port of the main amplifier and the combination node, an auxiliary output network connected between an output port of the auxiliary amplifier and the combination nod, and a merging matching network connected between the combination node and a radio frequency output port of the Doherty amplifier, where the merging matching network is configured for the node impedance at the combination node being a complex impedance, and the main output network and the auxiliary output network are configured for the node impedance matching with goal load impedances of the main amplifier and the auxiliary amplifier.
    Type: Application
    Filed: November 1, 2022
    Publication date: May 1, 2025
    Applicant: SUZHOU WATECH ELECTRONICS CO., LTD.
    Inventors: Haoyu LIU, Shuangshuang ZHENG, Liang LIN
  • Publication number: 20250096730
    Abstract: Disclosed are a power amplifier and a method for controlling a power amplifier. The method includes providing an input signal to the first amplification path and the second amplification path; and supplying a first DC bias voltage and a second DC bias voltage to a control port of the third transistor and a control port of the fourth transistor respectively, where current conduction trenches of the third transistor and the fourth transistor comprise same materials and the first DC bias voltage is higher than the second DC bias voltage.
    Type: Application
    Filed: March 27, 2023
    Publication date: March 20, 2025
    Applicant: SUZHOU WATECH ELECTRONICS CO., LTD.
    Inventors: Haoyu LIU, Mengsu YANG, Liang LIN
  • Publication number: 20250063760
    Abstract: Disclosed are a lateral silicon carbide junction gate field effect transistor (SiC-JFET) device and a manufacturing method thereof. The lateral SiC-JFET device includes a base; a source and a drift region formed on the base in sequence; a first source contact region, a second source contact region, and a channel region formed on the source in sequence; and a gate formed on the channel region; where the channel region and the drift region are independent structures respectively. The embodiments of the present disclosure solved the technical problem that the adjustment of the breakdown voltage of the conventional lateral SiC-JFET device is limited by the size of the channel region.
    Type: Application
    Filed: July 10, 2024
    Publication date: February 20, 2025
    Applicant: SUZHOU WATECH ELECTRONICS CO., LTD.
    Inventor: Changchang WANG