Abstract: A process chamber which may be operated as follows: mounting substrates in a substrate carrier; loading the substrate carrier into a vacuum chamber and mating the substrate carrier with an upper gas manifold and a lower gas manifold; providing and maintaining a vacuum environment within the vacuum chamber; making electrical contact to an at least one electrically-resistive heater; heating the substrates to a process temperature by flowing current through the at least one electrically-resistive heater; and while heating the substrates, flowing process gas through odd numbered channels from the upper gas manifold to the lower gas manifold, and simultaneously flowing process gas through even numbered channels from the lower gas manifold to the upper gas manifold; wherein the process gas comprises an inert gas and the substrates are being thermally annealed, or wherein the process gas is a dopant gas and the substrates are being doped.

Abstract: A system for depositing thin single crystal silicon wafers by epitaxial deposition in a silicon precursor depletion mode with cross-flow deposition may include: a substrate carrier with low total heat capacity, high emissivity and small volume; a lamp module with rapid heat-up, efficient heat production, and spatial control over heating; and a manifold designed for cross-flow processing. Furthermore, the substrate carrier may include heat reflectors to control heat loss from the edges of the carrier and/or heat chokes to thermally isolate the carrier from the manifolds, allowing independent temperature control of the manifolds. The carrier and substrates may be configured for deposition on both sides of the substrates—the substrates having release layers on both sides and the carriers being configured to have equal process gas flow over both surfaces of the substrate. High volume may be addressed by a deposition system comprising multiple mini-batch reactors.

Abstract: A CVD reactor for single sided deposition of material on substrates, may comprise: an upper gas manifold and a lower gas manifold; a substrate carrier comprising a gas tight rectangular box open on upper and lower surfaces, a multiplicity of planar walls across the width of the box, the walls being equally spaced in a row facing each other and defining a row of channels within the box, the walls comprising mounting fixtures for a plurality of substrates and at least one electrically resistive heater element; and clamps within the vacuum chamber for making electrical contact to the at least one electrically resistive heater element; wherein the upper gas manifold and the lower gas manifold are configured to attach to the upper and lower surfaces of the substrate carrier, respectively, connect with upper and lower ends of the channels, and isolate gas flows in odd numbered channels from gas flows in even numbered channels, wherein the channels are numbered in order along the row, and wherein the gas flows compr

Abstract: A CVD reactor for deposition of silicon carbide material on silicon carbide substrates, may comprise: an upper gas manifold and a lower gas manifold; and a substrate carrier comprising a gas tight rectangular box open on upper and lower surfaces, a multiplicity of planar walls across the width of the box, the walls being equally spaced in a row facing each other and defining a row of channels within the box, the walls comprising mounting fixtures for a plurality of substrates and at least one electrically resistive heater element; wherein the upper gas manifold and the lower gas manifold are configured to attach to the upper and lower surfaces of the substrate carrier, respectively, connect with upper and lower ends of the channels, and isolate gas flows in odd numbered channels from gas flows in even numbered channels, wherein the channels are numbered in order along the row; and wherein said electrically resistive heater elements and said mounting fixtures are coated with a material able to withstand exposu

Abstract: Methods and equipment for the removal of semiconductor wafers grown on the top surface of a single crystal silicon substrate covered by a porous silicon separation layer by using IR irradiation of the porous silicon separation layer to initiate release of the semiconductor wafer from the substrate, particularly at edges (and corners) of the top surface of the substrate.