Abstract: An apparatus, computer-readable medium, and computer-implemented method for parallelization of a computer program on a plurality of computing cores includes receiving a computer program comprising a plurality of commands, decomposing the plurality of commands into a plurality of node networks, each node network corresponding to a command in the plurality of commands and including one or more nodes corresponding to execution dependencies of the command, mapping the plurality of node networks to a plurality of systolic arrays, each systolic array comprising a plurality of cells and each non-data node in each node network being mapped to a cell in the plurality of cells, and mapping each cell in each systolic array to a computing core in the plurality of computing cores.
Abstract: Representative embodiments are disclosed for a rapid and highly parallel decompression of compressed executable and other files, such as executable files for operating systems and applications, having compressed blocks including run length encoded (“RLE”) data having data-dependent references. An exemplary embodiment includes a plurality of processors or processor cores to identify a start or end of each compressed block; to partially decompress, in parallel, a selected compressed block into independent data, dependent (RLE) data, and linked dependent (RLE) data; to sequence the independent data, dependent (RLE) data, and linked dependent (RLE) data from a plurality of partial decompressions of a plurality of compressed blocks, to obtain data specified by the dependent (RLE) data and linked dependent (RLE) data, and to insert the obtained data into a corresponding location in an uncompressed file.
Type:
Grant
Filed:
June 26, 2015
Date of Patent:
April 19, 2016
Assignee:
Sviral, Inc.
Inventors:
Paul L. Master, Frederick Curtis Furtek, Kim Knuttila, L. Brian McGann
Abstract: A hardware task manager for an adaptive computing system. The task manager indicates when input and output buffer resources are sufficient to allow a task to execute. The task can require an arbitrary number of input values from tasks. Likewise, output buffers must also be available before the task can start to execute and store results. The hardware task manager maintains a counter associated with each buffer. For input buffers, a negative value for the counter means that there is no data in the buffer and the buffer is not ready and the associated task cannot run. Predetermined numbers of bytes, or “units,” are stored into the input buffer and an associated counter is incremented. When the counter value transitions from a negative value to a zero the high-order bit of the counter is cleared indicating the input buffer has sufficient data and is available to be processed.
Type:
Grant
Filed:
June 11, 2012
Date of Patent:
July 15, 2014
Assignee:
Sviral, Inc.
Inventors:
W. James Scheuermann, Eugene B. Hogenauer
Abstract: A hardware task manager for managing operations in an adaptive computing system. The task manager indicates when input and output buffer resources are sufficient to allow a task to execute. The task can require an arbitrary number of input values from one or more other (or the same) tasks. Likewise, a number of output buffers must also be available before the task can start to execute and store results in the output buffers. The hardware task manager maintains a counter in association with each input and output buffer. For input buffers, a negative value for the counter means that there is no data in the buffer and, hence, the respective input buffer is not ready or available. Thus, the associated task can not run. Predetermined numbers of bytes, or “units,” are stored into the input buffer and an associated counter is incremented.
Type:
Application
Filed:
June 11, 2012
Publication date:
May 9, 2013
Applicant:
Sviral, Inc.
Inventors:
W. James Scheuermann, Eugene B. Hogenauer