Abstract: A memory cell is provided in an isolation layer on a side of a substrate, the isolation layer includes an accommodation hole, the memory cell includes a channel layer, an insulating dielectric layer, a gate layer and a gate dielectric layer. The channel layer includes a first channel and a second channel spaced apart and stacked, the first channel is provided in the accommodation hole, the second channel is at least partially provided in the accommodation hole, the gate layer includes a first gate and a second gate, the first gate is formed within the first inner hole and directly or indirectly connected to the second channel, and the second gate is at least partially formed within the second inner hole; and a gate dielectric layer is formed between the gate layer and the channel layer.

Abstract: A wafer processing device includes a processing assembly, a wafer boat loading and unloading chamber, a wafer boat base located in the wafer boat loading and unloading chamber, a wafer loading and unloading chamber, a wafer transfer assembly located within the wafer loading and unloading chamber, a plurality of isolation chambers, a plurality of wafer boats, and a transfer device, and a front switching door is provided between the isolation chamber and the wafer boat loading and unloading chamber, and a rear switching door is provided between the isolation chamber and the wafer boat loading and unloading chamber. The transfer device is used to transfer the wafers in the interiors of the wafer loading and unloading chamber and the isolation chamber, and transfer the wafers in the interior of the wafer boat loading and unloading chamber and the isolation chamber.

Abstract: A method is provided for manufacturing a semiconductor structure. The method includes providing a through hole penetrating a stacked layer and exposing a surface of an interconnecting conductive layer; forming a side wall material layer covering at least a side wall and a bottom of the through hole; forming a protective material layer covering the side wall material layer; performing thermal processing on the protective material layer, to cause the protective material layer to implement a material phase change process; etching and removing materials located at the bottom of the through hole to expose the surface of the interconnecting conductive layer, covering the side wall of the through hole, of the side wall material layer as a side wall layer, and taking a remaining protective material layer covering the side wall layer as a protective layer. Working performance of the semiconductor structure is improved.

Abstract: Disclosed are a semiconductor structure and a fabrication method thereof. The semiconductor structure includes a substrate; a gate structure, disposed on the substrate; a channel pillar, disposed on the substrate and extending through the gate structure in the longitudinal direction; a spacer, extending longitudinally between the sidewall of the channel pillar and the gate structure; a compensation layer, filling the void between the channel pillar and the gate structure at the bottom position of the spacer. The present disclosure facilitates improving the operating performance of the semiconductor structure.