Abstract: A method and apparatus for playing a word game with two players, wherein a programmed processor allows: a. a first player to select a secret word of a predetermined length by choosing a word from among the words in a predetermined dictionary, the secret word to be guessed by the second player within a predetermined number of guesses; b. the second player to make a guess of the secret word; c. the first player to indicate to the second player the letters in the guessed word that are in the secret word; d. to repeat steps b. and c. until the secret word is guessed or the predetermined number of guesses have been made; and e. wherein the first player is a human, and the second player is a computer.

Abstract: A symbolic language data processing system comprises a sequencer unit, a data path unit, a memory control unit, a front-end processor, an I/O and a main memory connected on a common Lbus to which other peripherals and data units can be connected for intercommunication. The system architecture includes a novel bus network, a synergistic combination of the Lbus, microtasking, centralized error correction circuitry and a synchronous pipelined memory including processor mediated direct memory access, stack cache windows with two segment addressing, a page hash table and page hash table cache, garbage collection and pointer control, a close connection of the macrocode and microcode which enables one to take interrupts in and out of the macrocode instruction sequences, parallel data type checking with tagged architecture, procedure call and microcode support, a generic bus and a unique instruction set to support symbolic language processing.

Abstract: A symbolic language data processing system comprises a sequencer unit, a data path unit, a memory control unit, a front-end processor, an I/O and a main memory connected on a common Lbus to which other peripherals and data units can be connected for intercommunication. The system architecture includes a novel bus network, a synergistic combination of the Lbus, microtasking, centralized error correction circuitry and a synchronous pipelined memory including processor mediated direct memory access, stack cache windows with two segment addressing, a page hash table and page hash table cache, garbage collection and pointer control a close connection of the macrocode and microcode which enables one to take interrupts in and out of the macrocode instruction sequences, parallel data type checking with tagged architecture, procedure call and microcode support, a generic bus and a unique insruction set to support symbolic language processing.

Abstract: A parallel processing system is receptive of a program and has at least two processors connected in parallel to a shared main memory. Each processor executes instructions of the program which includes side-effecting instructions which modify the contents of a location in main memory and functional instructions which reference locations in main memory. The program is compiled into a series of independent instruction blocks each of which includes predominantly functional instructions and terminates in a side-effecting instruction and the processors execute the blocks in parallel.

Abstract: A method and device for converting movement of an optical mouse on a surface having any random surface pattern of relatively light and dark areas separated by edges to electrical signals representing a direction of motion relative to two non-parallel axes. A plurality of prechargeable photon sensors are disposed on the mouse in a row along each axis and facing the surface periodically. The presence of an edge is periodically sensed in at least one preselected portion of each row of sensors, defining a sensor state for each axis for each period upon the sensing of an absence of an edge. Successive sensor states are compared to determine if movement has occurred relative to each axis and a signal representative of the movement determined is produced.

Abstract: A programmable clock generator includes programmable logic arrays implementing a shift register and control circuits elements connected between the inputs and outputs of the shift register elements and responsive to a code applied thereto for skipping preselected shift register elements during shifting. At least one JK flip-flop is receptive of timing signals from non-skipped shift register elements at the J and K inputs thereof to produce a clock signal at the output thereof.

Abstract: A computer monitor is provided with a chassis including a base, a rear support fixed to the base and extending vertically upwardly therefrom, and a front support connected to a cathode-ray tube. The front support and the cathode-ray tube are mounted above the base and spaced apart therefrom for pivotal movement of the front support and cathode-ray tube relative to the base and rear support about a pivot axis disposed at the upper front portion of the monitor. The monitor can be releasably maintained in any one of a plurality of angular positions. The monitor housing comprises a first section surrounding the base and rear support and a second section completely detached from the first section and surrounding the front support.

Abstract: A light pipe for use in an optical mouse comprises a block of light transmitting fibers comprising a plurality of parallel light transmissive regular polygonal fiber cores each surrounded by light transmissive cladding having a lower index of refraction than the core. The ratio of the width of the core to the thickness of the cladding ranges from 4 to 24.