Abstract: A shared memory computing architecture (300) has M interconnect masters (350, 351, 352, 353, 354), one interconnect target (370), and a timeslot based interconnect (319). The interconnect (319) has a unidirectional timeslot based interconnect (320) to transport memory transfer requests with T timeslots and a unidirectional timeslot based interconnect (340) to transport memory transfer responses with R timeslots. For each of the R timeslots, that timeslot: corresponds to one memory transfer request timeslot and starts at least L clock cycles after the start time of that corresponding memory request timeslot. The value of L is >=3 and <T. Interconnect target (370) is connected to interconnect (319). Each interconnect master (350, 351, 352, 353, 354) is connected to interconnect (319).

Abstract: A shared memory computing device that has a system interconnect, an on-chip random access memory (RAM), at least one sub-computing device and a peripheral. The RAM is connected to the system interconnect. Each sub-computing device has: (a) a first local interconnect, (b) an interconnect master connected to a local interconnect of the sub-computing device; and (c) an interconnect bridge; in which the interconnect master is adapted to issue memory transfer requests to the RAM over that bridge. The peripheral comprises a target port which is connected to the first local interconnect of the first of the at least one sub-computing devices; and a first interconnect master port which is adapted to issue memory transfer requests to the RAM. The interconnect master of the first of the at least one sub-computing devices is adapted to issue memory transfer requests to the first peripheral.

Abstract: A bidirectional interconnect for transporting memory transfer requests and their corresponding memory transfer responses that has: (a) a unidirectional interconnect to transport memory transfer requests; and (b) a unidirectional interconnect to transport memory transfer responses. The write memory transfer responses include at least a copy of the data to be written of the corresponding write memory transfer request. The memory transfer responses may also include a copy of the corresponding memory transfer request. This interconnect is particularly well suited for use in cache-coherent real-time computing architectures that have peripherals.

Abstract: A shared memory computing device optimised for worst case execution time analysis that has at least one interconnect master, N cache modules and N processor cores. Each cache module has a finite state machine that employs an update-type cache coherency policy. Each processor core is assigned a different one of the N fully associative cache modules as its private cache. Furthermore, the execution time of memory transfer requests issued by each of the N processor cores is not modified by: (a) the unrelated memory transfer requests issued by any of the other N processor cores; or (b) the unrelated memory transfer requests issued by at least one other interconnect master.

Abstract: A shared memory computing architecture (300) has M interconnect masters (350, 351, 352, 353, 354), one interconnect target (370), and a timeslot based interconnect (319). The interconnect (319) has a unidirectional timeslot based interconnect (320) to transport memory transfer requests with T timeslots and a unidirectional timeslot based interconnect (340) to transport memory transfer responses with R timeslots. For each of the R timeslots, that timeslot: corresponds to one memory transfer request timeslot and starts at least L clock cycles after the start time of that corresponding memory request timeslot. The value of L is >=3 and <T. Interconnect target (370) is connected to interconnect (319). Each interconnect master (350, 351, 352, 353, 354) is connected to interconnect (319).