Abstract: The touch panel controller is connected with a touch panel having a plurality of drive electrodes, a plurality of detection electrodes, and a plurality of capacitance components formed at intersections of the drive and detection electrodes. A two-edge detection mode is adopted for the touch panel controller, in which signals arising on each detection electrode in synchronization with rising and falling edges of a drive pulse output to the drive electrodes, and alternately changing in polarity are accumulated in the integration circuit in terms of absolute value components. The integration circuit switches the connection of the integration capacitance between an input and an output before the drive pulse edge changing. The touch panel controller contributes to the shortening of the time for touch detection by the touch panel and the increase of the accuracy of touch detection.

Abstract: A display driver that receives display line data of plural display lines to perform drive control on a display panel includes a line memory for storing display line data which is supplied from the outside. The display driver includes a logic circuit that controls write and read-out of the display line data in and from the line memory, and sorts pixel data of the display line data using read out data from the line memory, to generate display drive data. Drive circuits drive the display panel in units of display lines based on the drive data which is output from the logic circuit. The drive circuits are separately arranged on both sides of the logic circuit and the line memory which are interposed therebetween. The storage capacity of the line memory corresponds to the number of lines smaller than the number of display lines of a display frame.

Abstract: A junction barrier Schottky diode is formed by shifting second semiconductor regions of a second conductivity type in a staggered shape in a first semiconductor region of a first conductivity type so that pn junction regions are formed at predetermined distances between the second semiconductor regions and the first semiconductor region. A third semiconductor region of the first conductivity type is formed between the second semiconductor regions in order to form a Schottky junction region. An electrode is formed on the second and third semiconductor regions. The second semiconductor regions arranged at equal distances in an X direction are formed in a plurality of columns in a Y direction. An amount of shift between adjacent columns in the X direction is set such that a Y-direct ion distance between the second semiconductor regions in the different columns is larger than an X-direction distance between the second semiconductor regions in each column.

Abstract: A display control device and technique for controlling displays on a display unit, in which a plurality of display segments are two-dimensionally arranged (e.g. a dot matrix type display unit), is provided. The technique is effectively applicable to a write data latch circuit of a memory for storing display data in the display control device, such as, for example, a liquid crystal display control device, a mobile electronic apparatus, etc. A display drive control technique for controlling a moving picture display mode of a display device is also provided. The display drive control circuit controls a picture display mode of a display device for displaying still pictures and moving pictures to a liquid crystal display device, such as, for example, a dot matrix type display devices, an organic EL display device, etc.

Abstract: Detection circuits cause a power supply circuit to start an initialization sequence by detecting abnormal behavior where an external power supply voltage is cut off, the power supply circuit generating a first internal power supply voltage from a first external power supply voltage and generating a second internal power supply voltage from a second external power supply voltage higher than the first external power supply voltage in terms of an absolute value, and an auxiliary amplifier that makes up for a drop in the first internal power supply voltage, using the second external power supply voltage as an operation power supply after detecting the abnormal behavior of the first external power supply voltage. A sample and hold circuit of a reference voltage of the auxiliary amplifier is configured in a hold state after detecting the abnormal behavior of the first external power supply voltage.

Abstract: A common touch panel controller is used for performing touch detection by driving both a touch panel superimposed on a display panel of a touch panel display portion for display, and a touch sensor superimposed on a touch key pattern of a touch key input portion for buttons. A control circuit capable of switching detection characteristics of a detection circuit common to the both in accordance with detection from the touch panel display portion and detection from the touch key input portion is adopted in the touch panel controller.

Abstract: A liquid crystal display driver IC includes a plurality of communication interface circuits, a plurality of driving circuits which drive a plurality of source lines, and a selector circuit. In order to secure a necessary band-width, a necessary number of circuits, among the plurality of communication interface circuits, is connected in parallel to the communication channels, and an unused circuit is suspended. The selector circuit selectively controls to which one of the plurality of driving circuits each of a plurality of image data outputs respectively received from the connected communication interface circuits is supplied.

Abstract: An apparatus and method for dynamically controlling power of a device. In one embodiment, the apparatus includes a first circuit and a second circuit for generating a clock signal, wherein a frequency of the clock signal is dependent on a control voltage provided to the second circuit. A third circuit is coupled to receive the control voltage and is configured to adjust power consumed by the first circuit based on the control voltage.

Abstract: A semiconductor wafer includes circuit integration regions each incorporating an integrated circuit and guard rings disposed to surround the circuit integration regions, respectively. A scribe region disposed between every adjacent two of the guard rings. An element and a pad electrically connected to the element are disposed in the scribe region. A groove is disposed along a corresponding guard ring on a front surface of the semiconductor wafer between the pad and the corresponding guard ring. The distance between the groove and the pad is varied along the corresponding guard ring.

Abstract: A clock data recovery (CDR) circuit includes a sampling circuit, a synchronization circuit that synchronizes a frequency of an oscillation clock signal from an oscillation circuit with a frequency of input data of a specific pattern which is sampled in the sampling circuit, and synchronizes a phase of the oscillation clock signal with a phase of the sampled input data, and a data pattern recognition circuit that detects whether the input data sampled in the sampling circuit has a specific pattern. The data pattern recognition circuit starts an operation for detecting whether the input data has a specific pattern in response to a frequency lock start instruction. The synchronization circuit starts an operation for synchronizing the frequency on condition that it is determined by the data pattern recognition circuit that the input data has a specific pattern.

Abstract: In a manufacturing method for a semiconductor device provided with a MONOS-type FET for a non-volatile memory and high-voltage and low-voltage MOSFETs, a groove having a predetermined depth is formed in a region in which the high-voltage MOSFET on a semiconductor substrate is formed, and an oxide film serving as a gate insulating film of the high-voltage MOSFET is formed within the formed groove by thermal oxidation. Thereafter, a gate electrode film of the low-voltage MOSFET is formed on the entire surface of the semiconductor substrate. Thereafter, a region for the MONOS-type FET is opened, the semiconductor surface of the semiconductor substrate is exposed, and a first potential barrier film, a charge storage film, and a second potential barrier film are sequentially deposited, to thereby form a charge storage three-layer film. Agate electrode film of the MONOS-type FET is formed on the formed charge storage three-layer film.

Abstract: A gate oxide film is formed in a region having a MOSFET on a semiconductor substrate formed therein, and a first polysilicon film serving as a gate electrode of the MOSFET is further formed. Thereafter, a charge storage three-layer film is formed by opening a region having a MONOS type FET formed therein, exposing a semiconductor surface of the semiconductor substrate, and sequentially depositing a first potential barrier film, a charge storage film, and a second potential barrier film. In this case, before the charge storage three-layer film is formed, an anti-oxidation film is formed on the first polysilicon film.

Abstract: A clock data recovery (CDR) circuit is provided with a circuit that updates a locked oscillation frequency, with a small loop gain, after phase lock based on a phase-locked loop circuit for a frequency-locked frequency is completed by a frequency-locked loop circuit or during a phase lock operation. Since the locked oscillation frequency is updated with a small loop gain, it is possible to correct a fluctuation in a frequency of an oscillation circuit in the frequency-locked loop circuit without oscillating a phase-locked loop undesirably even during a phase lock operation.

Abstract: A display device includes a boosting power supply circuit, a logic circuit and a charge transport path. The boosting power supply circuit generates a boosted power supply voltage by boosting an analog power supply voltage. The logic circuit is responsive to a decrease in a voltage level on at least one of power supply lines to which analog and logic power supply voltages are supplied for controlling a source line drive circuitry and a gate line drive circuitry to discharge charges accumulated in the display panel. The charge transport path is configured to transport charges from a power supply line on which the boosted power supply voltage is generated to a power supply line which supplies an internal logic power supply voltage to the logic circuit in response to the decrease in the voltage level on the at least one of the first and second power supply lines.

Abstract: The SRAM memory cell includes a metal wiring line having a titanium or tantalum film in a bottom layer, and a via having a tungsten plug. The via is arranged on the metal line following a layout rule which permits the misalignment. In arranging the upper-layer via with a tungsten plug on the metal line, one side of the via is disposed to be adjacent to one end of the metal line with a margin smaller than an alignment accuracy, and the lower-layer via is laid out far away from the end of the metal line as possible. The reduction in the yield, caused by the problem of the contact with the lower-layer via being broken or increased in resistance at occurrence of misalignment, can be suppressed.

Abstract: An image processing circuit includes a scaling processing section having interpolation coefficient inputs, an interpolation coefficient rearrangement section and an interpolation coefficient feeding section. The interpolation coefficient feeding section feeds first interpolation coefficients to the interpolation coefficient rearrangement section. The interpolation coefficient rearrangement section is configured to feed interpolation coefficients selected from the first interpolation coefficients and second interpolation coefficients obtained by subtracting the first interpolation coefficients from a predetermined value, respectively, to the respective interpolation coefficient inputs of the scaling processing section in response to coordinates of a target pixel of the output image.

Abstract: The driver IC includes: a control circuit operable to perform control for creating the timing of detection by a touch panel in a non-display drive period during which the action of a drive circuit remains stopped, and for creating a display drive period during which the drive circuit drives the display panel, and the non-display drive period; and a data RAM operable to hold display data of more than one display line, but smaller than one display frame in capacity. The control circuit performs control for alternately creating the display and non-display drive periods by repeating a memory-addressing operation for writing display data supplied from outside into the RAM and reading the display data from the RAM at a speed faster than the writing speed to provide the read data to the drive circuit two or more times in a period of one display frame according to a wraparound method.

Abstract: A semiconductor device includes: a semiconductor chip having a main face which has a pair of long sides parallel to each other and a pair of short sides orthogonal to the pair of long sides; first bumps arrayed in a first bump placement region of the semiconductor chip, the first bump placement region being positioned along one of the pair of long sides; second bumps arrayed in a second bump placement region of the semiconductor chip, the second bump placement region being positioned along the other of the pair of long sides; first power lines disposed in a region between the first bump placement region and the second bump placement region, the first power lines extending in a direction parallel to the pair of long sides; and third bumps integrated on the semiconductor chip. Each of the third bumps provides short-circuiting of the first power lines.

Abstract: A liquid crystal display device includes a liquid crystal display panel; and a driver driving the liquid crystal display panel. The liquid crystal display panel includes: a first substrate on which subpixels each including a pixel electrode are integrated; and a second substrate opposed to the first substrate, a plurality of common electrodes being formed on the second substrate. The display region of the liquid crystal display panel is divided into a plurality of sections respectively corresponding to the common electrodes. When a partial display in which an image is selectively displayed in a selected section is performed, the liquid crystal driver drives the common electrode corresponding to the selected section to a predetermined common voltage level, sets the common electrodes corresponding to the non-selected sections to a predetermined reference level, and sets pixel electrodes of subpixels in the non-selected sections to the reference voltage level.

Abstract: A semiconductor device including a display driving circuit that drives a display panel, a touch detection signal driving circuit that applies a touch detection signal to a touch sensor, and a touch state detection circuit that receives a signal obtained by observing the touch sensor is configured as follows. A connection switching circuit that switches connection between a terminal and an internal circuit is included therein. The connection switching circuit switches connection with the terminal by selecting one of at least two of the display driving circuit, the touch detection signal driving circuit and the touch state detection circuit. A protection circuit which is capable of changing a protection voltage level is connected to the terminal, and the protection voltage level varies depending on the signal amplitude of the circuit selected by the connection switching circuit.