Abstract: Provided is a circuit driving method which can minimize a problem generated by a peak current in a display memory device. Data to be transferred to a display panel is read out from a memory cell array storing binary information. The read-out data are stored in source data buffers and a plurality of source data buffers are divided into several groups and then enabled. An enable signal for each group is derived from a single enable signal and has a different delay time. In the source data buffers delayed by each group and enabled, consumption of current is distributed so that a peak current flowing in the overall source data buffer is lowered. Thus, reliability in the operation of a circuit is improved and the operation speed increases.

Abstract: A multilevel voltage generator includes a first positive voltage generator generating a first output voltage using a first capacitor which receives a reference voltage and is charged to a voltage level corresponding to two times of the reference voltage, a second positive voltage generator generating a second output voltage and a third output voltage using a second capacitor and a third capacitor which receive the first output voltage and are charged to voltage levels corresponding to predetermined multiples of the reference voltage, and a negative voltage generator generating a fourth output voltage having predetermined negative voltage levels using a fourth capacitor which receives the reference voltage, the second output voltage, or the third output voltage and is charged to a voltage level corresponding to a negative voltage of the second or third output voltage.

Abstract: A multi-port static random access memory for reducing an occupation area of a layout memory cells on a substrate having the improvements from a first plurality of metal electrode layers on a first plurality of active regions included in one unit cell and in other unit cell neighbored to the corresponding one unit cell of the first plurality of metal electrode layers being commonly connected to the power supply source, comprises: a second plurality of the metal electrode layers on second plurality of the active regions and to be independently and separately connected to the power supply source, by every one unit cell in cell array.