Abstract: A process for producing a small shallow-depth high-performance bipolar structure having low parasitic capacitance is disclosed wherein an active base region of a P-type material is first defined in a substrate, a portion of which is of N-type material in a device formation area surrounded by an isolating oxide regions, such as trenches or the like. An N-doped polysilicon layer is then defined over the active base region and over field oxide regions located atop the isolating trenches. This N-poly region, when treated, will provide an interdigitated collector with self aligning emitter region aligned over the active base region. After appropriate spaced isolation layers are placed, a P-poly layer is laid down and heat treated to cause the P-type doping material to diffuse into the substrate contact to the active base region. A thin buried collector layer, approximately 1.

Abstract: A high density ASIC cell provides customization solely at the polysilicon #2, insulator #3 levels. High density is achieved by permitting a metal #1 trace to traverse an underlying transistor, without requiring space between adjacent transistors to facilitate traversing interconnects. Oversized collector and emitter traces at the polysilicon #1 level make downward contact with the collector and base regions of the underlying transistor, and provide redundant upward contact with collector and emitter polysilicon #2 traces. Contact between the transistor base and a base polysilicon #2 trace is also made. The polysilicon #2 emitter, base and collector traces provide a replicated, unvarying pattern that preferably defines a 3.times.3 matrix of potential contact points for overlying metal #1 traces to contact the underlying transistor's emitter, base and collector. A metal #1 trace can traverse this 3.times.3 matrix simply by not providing openings in the insulating #3 layer beneath the traverse.

Abstract: A DC-coupled active pull-down ECL circuit ("LS-APD") has a pull-down drive that self-adjusts to load conditions. A current source sinks emitter current from first and second push-pull transistors. The input signal is coupled to the base of the first transistor, whose inverted collector signal is coupled to the base of a pull-up transistor whose emitter is the LS-APD output voltage node. (A non-inverting configuration provides the input signal to the base of the second transistor.) The pull-up transistor is coupled between the upper rail and the second transistor's collector load resistor. A pull-down transistor has its base coupled to the second transistor's collector, its collector coupled to the LS-APD output node, and its emitter coupled to a node receiving a regulated Vreg voltage. As load capacitance increases, the output voltage takes longer to drop sufficiently to nearly turn-off the pull-down transistor.

Abstract: The present invention relates to a modified emitter coupled logic circuit which includes a differential logic stage and an emitter-follower output stage. An active pull-down circuit and a constant voltage source are included in the output stage of this circuit to allow the output of the circuit to switch from a high level to a low level at approximately the same speed as the output can switch from a low level to a high level. A particular embodiment of the present invention provides a constant voltage source comprising an operational amplifier, a reference potential generating circuit and a constant voltage signal adjusting circuit.

Abstract: A bit line discharge and sense circuit is provided for use with a static RAM that includes a row and column array of memory cells addressable via first and second bit lines and also a row select line. Each memory cell includes a transistor pair, wherein the first and second bit lines are coupled to an emitter of a first and second transistor comprising the transistor pair. The invention couples two current sources via the associated bit lines to the emitter of each transistor in the cell. A first current source is coupled when the cell is selected and provides a first current value having a bit line capacitance discharge current component and a first transistor read current component. A second current source is coupled to the same emitter when the cell is selected, and provides a lower current value. The first current source rapidly discharges capacitance associated with the associated bit line on the selected cell.

Abstract: Bipolar devices on a common substrate are formed in tubs defined by a sinker that is self-aligning with the isolating trench and provides a relatively low vertical resistance contact from a surface contact to the underlying buried layer. In a first embodiment, the isolating trench initially is defined only down to the top surface of the buried layer. The trench walls are then doped, and the dopant allowed to diffuse laterally through the trench sidewalls. The resultant sinker is self-aligned with the isolating trench. The trench depth is then further increased to a desired depth preferably penetrating into the substrate. Thereafter, a bipolar device is formed in the tub, preferably with the device collector adjacent the trench and thus aligned with the sinker. In a second embodiment, an opening is formed in the surface oxide defining the area where the trench (when formed) will be cut.

Abstract: A substrate tap is incorporated in an integrated circuit which comprises a plurality of transistors formed in isolated device regions in a substrate material comprising a layer of N-type material over a layer of P-type material. The isolated device regions are defined by isolating slots extending down through said N-type material and into the P-type material. The trench for each substrate tap extend down to said P-type material and has an oxide layer lining the sidewalls of trench, a doped polysilicon layer covering the sides and bottom of said trench, and a doped implant or diffused region formed at the base of and in contact between the tap and the substrate. The substrate beneath the devices is connected to a negative potential to isolate the devices on said substrate. Preferably, the substrate tap includes a silicide layer formed over said polysilicon layer to enhance contact to said doped implant region.

Abstract: A switched load diode cell has been developed wherein first and second multi-emitter NPN transistors are provided having bases cross coupled to the other's collectors in typical latch fashion as shown in FIG. 5. A PN diode is provided having an anode coupled to the select line through a load resistor and a cathode coupled to the collector of each associated multi-emitter transistor. A parasitic lateral PNP transistor associated with the PN diode is provided having an emitter coupled to the select line through the same load resistor and a collector connected to the base of the associated multi-emitter transistor. A relatively low resistance load of about 500.OMEGA. is connected between the common node which consists of the emitter of the parasitic lateral PNP transistor and the anode of the PN diode and the select line. In this way, a switched load diode cell is provided.

Abstract: A sinker which is self-aligned with the oxide isolating trench which is used to define the tub in which the complete bipolar device is located. In a preferred approach to the process for forming the sinker of this invention, little additional diffusion of the sinker occurs during subsequent processing, whereby an effective sinker, aligned with the collector of the bipolar device, is achieved without additional masking steps.