Abstract: A dynamic memory management method for layout verification tools that maximizes main memory usage and minimizes required disk storage capacity. Layout data generated during each given geometric operation is retained in main memory at the end of the given geometric operation. At the beginning of each new (current) geometric operation, an estimated amount of main memory required to perform the current geometric operation at peak processing speed is determined. When insufficient available main memory is available, a Central Balancer Module determines whether previously generated layout data can be moved from main memory to disk storage. Layout data file(s) are then selected based on minimizing the amount of transferred layout data needed to provide the required estimated amount. A Distributed File Manager then transfers the selected layout data file(s) from main memory to disk storage, thereby facilitating execution of the current geometric operation at peak operating speed.

Abstract: The fault analysis problem is modelled by automatically creating additional properties (fault properties) and constraints based on a plurality of injected faults and existing user assertions. These fault properties and constraints are sent to formal verification in a single run to qualify all of the faults together, rather than sequentially checking each fault in a separate formal verification run.

Abstract: A system including a user interface, a memory, and a processor configured to perform operations stored in the memory is disclosed. The operations may include receiving an application specification including an application algorithm, and extracting from the application algorithm a first and a second node. The first node may include a first component of the application algorithm, and the second node may include a second component of the application algorithm that may be different from the first component. The operations may include analyzing execution dependency of the first node on the second node. The analyzing execution dependency may include analyzing computational requirements, bandwidth requirements, and input trigger requirements of the first node and the second node based on parallelism of available resources.

Abstract: A cell-aware defect characterization method includes partitioning a multibit cell netlist file into multiple single-bit partition netlist files, and then generating a cell-aware test model for each partition netlist file. Partitioning is performed such that each partition netlist file includes a corresponding flip-flop along with input, output and control pins that are operably coupled to the input, output and control terminals of the corresponding flip-flop, and all active, passive and parasitic circuit elements that are coupled in the signal paths extending between the corresponding flip-flop and the input/output/control pins. Shared resources (e.g., clock or scan select pins and associated signal lines) that are utilized by two or more flip-flops are included in each associated partition. The partitioning process is performed using either a structural back-tracing approach or a logic simulation approach.

Abstract: A method for designing a standard cell, e.g. a multi-bit flip-flop, can include identifying a first set of transistors. This first set functions to source power or ground to circuits of the standard cell. A second set of transistors can be determined and correlated. This second set forms at least part of the first set of transistors. Each correlated group in the second set of transistors receives identical signals, e.g. scan enable, reset, and/or set signals, and provides a same sourcing. A third set of transistors can then be created. This third set has fewer transistors than the second set. The second set of transistors can be deleted in the standard cell. The third set of transistors can be connected to the circuits of the standard cell. This method can significantly extend circuit consolidation to improve the area benefit of multi-bit standard cells.

Abstract: A circuit description, such as a hierarchical netlist, is obtained for an integrated circuit. Based on the circuit description, a treemap representation is rendered using blocks, nodes, and/or devices from the hierarchical netlist as objects, or leaves, in the treemap representation. Using a virtual layout, the leaves are positioned in the treemap representation independent of their physical layout. Circuit properties for the electronic design are also obtained using various methods such as a circuit simulator. The circuit properties are displayed to a user on the treemap representation.

Abstract: An apparatus having two or more parallel carry chain structures, each of the carry chain structures comprising a series of logical structures, where at least one of the logical structures within each of the carry chain structures has an associated input node, output node and carry node. The input node corresponds to a function input term, the output node corresponds to an output term of the function and the carry node corresponds to a carry value to a following logical structure in the series of logical structures.

Abstract: In various embodiments, each possible different instance of a repeated block can be concurrently modified for chip routing. Repeated blocks can be implemented where all instances of a repeated block are identical or substantially identical. Pin placement may be determined based on analysis of the I/O for all instances. The pin placement may be generated to be identical or substantially similar for all instances. Flyover blockages can be designed into repeated blocks to enable the global router to wire through the repeated block. Buffers and associated pins can be inserted into repeated block within the flyover space where the global router wires to the needed buffer through area pins.

Abstract: Apparatus, systems, and methods may include managing electrostatic discharge events in radio frequency identification (RFID) devices by using a semiconductor circuit having a non-aligned gate to implement a snap-back voltage protection mechanism. Such circuits may be formed by doping a semiconductor substrate to form a first conductive region as a well, forming one of a source region and a drain region in the well, depositing a layer of polysilicon on the substrate to establish a gating area that does not overlap the one of the source region and the drain region, and forming an integrated circuit including an RFID circuit that is supported by the substrate to couple to the one of the source region and the drain region to provide snap-back voltage operation at a node between the integrated circuit and the source or drain region. Additional apparatus, systems, and methods are disclosed.

Abstract: Roughly described, a method for mask data preparation is described, for use with a preliminary mask layout that includes a starting polygon, the vertices of the starting polygon including I-points (vertices of the starting polygon having an interior angle greater than 90 degrees), including steps of developing a rectilinear partition tree on at least the I-points of the starting polygon, and using the edges of the partition tree to define the partition of the starting polygon into sub-polygons for mask writing.

Abstract: Roughly described, assertion expressions are evaluated against the binary signal values of a circuit simulation in such a way as to be able to report status information at intermediate levels of assertion subexpressions. In one embodiment, the status information reported for an intermediate subexpressions contains the final status of that subexpression in response to a given assertion attempt, at least to the extent it has been determined by the end of the evaluation period (e.g. pass, fail or indeterminate). In another embodiment, the status information reported for an intermediate subexpression contains a tick-by-tick analysis of the activity within that subexpression. In another embodiment, the status information for a subexpression can also contain a tick-by-tick analysis of the activity of an operator of the subexpression. Other kinds and levels of detail at the subexpression level can be provided in various other embodiments.

Abstract: A method and apparatus for modeling using a hardware-software software co-verification environment is provided. An instruction set simulator is coupled to a simulator circuit to determine if the hardware design is correct. Specifically, the instruction set simulator acts as a “master” to the simulator circuit, thus providing a faster simulation environment. The simulator circuit contains a bus functional model, a hardware model, transfer memory, and the hardware design to be tested. The hardware model is designed to emulate a micro-controller. By disabling a processor within the hardware model, the speed of the simulation is restricted only by the speed of the instruction set simulator or the hardware design. Furthermore, the hardware design may be uncoupled from the simulator circuit in order to initialize the operating system.

Abstract: A simulation architecture and method having four major steps. Firstly, an input circuit description to be simulated is compiled into an initial circuit compilation as follows. The input circuit description is translated into an initial register transfer level (RTL) network representation comprised of sequential and/or combinational objects. Next, translation of the RTL network into a network of clusters is accomplished. In general, a cluster is a region of the circuit which has uniform simulation activity. The initial clustering process, by default, chooses an simulation mode for all clusters known as event-triggered cycle-based. The other possible simulation mode for a cluster, in accordance with the present invention, is oblivious-triggered cycle-based. The first major step completes with translating the network of clusters into simulatable object code which includes additional object code that generates activity data regarding each cluster during a simulation.

Abstract: A method and apparatus providing a graphical user interface (GUI) that automatically determines timing groups and path groups for a circuit representation. In a first GUI display level, the GUI displays each path group in the circuit and allows the user to change the timing constraints for each path group. In addition, the GUI indicates whether each timing group is activated by a rising or falling clock signal. In addition, the user can define subpaths of a path group. After timing analysis software has analyzed the circuit, by clicking on a timing group in the first GUI display level, the user can view a second GUI display level, which shows details of the paths in the indicated timing group. By clicking on a path in the second GUI display level, the user can view a third GUI display level, which shows a list of each of the elements in the indicated path.