Abstract: A current may be passed through a channel of an anti-fuse field-effect transistor (FET) to increase a temperature of a gate dielectric of the anti-fuse FET and change a rupture voltage of the gate dielectric of the anti-fuse FET from a first rupture voltage to a second rupture voltage. The gate dielectric may be ruptured by applying a first voltage between the gate dielectric and the channel of the anti-fuse FET, where the first voltage is between the first rupture voltage and the second rupture voltage.

Abstract: A first current may be passed through a channel of a fuse field-effect transistor (FET) to heat a gate of the fuse FET. A second current may be passed between a first gate terminal and a second gate terminal of the gate of the fuse FET to permanently degrade one or more electrical characteristics of the fuse FET.

Abstract: In an example, a multi-level data structure is defined including fine grid (FG) and coarse levels. The FG level is configured to store FG data of FG points. The coarse level is configured to store, for a respective chunk of FG points, compressed FG data and/or a pointer to corresponding FG data of the respective chunk. First chunks are identified by a graphics processing unit (GPU) and include each chunk of the FG points including one or more of: (i) that includes a FG point in a level set layer L0 (LSL0), and (ii) that neighbors a chunk that includes the FG point in the LSL0. Memory of the GPU is allocated for the first chunks that have respective compressed FG data to be decompressed. Level set values of the FG points in the LSL0 stored in the FG level in the allocated memory are updated by the GPU.

Abstract: A computer-implemented method including: providing a test template for a hardware system-under-test comprising one or more execution threads, wherein the test template comprises a branching instruction to a predetermined shared memory address accessible by at least some of the one or more execution threads; generating and storing, at the predetermined shared memory address, a sequence of instructions which conform to the test template; building, based, at least in part, on the test template, an executable image of a hardware exerciser, wherein the hardware exerciser is adapted to control a test cycle of the hardware system-under-test, and wherein the test cycle comprises at least generation and execution of a test; and executing the executable image of the hardware exerciser by at least a first execution thread of the one or more execution threads of the hardware system-under-test.

Abstract: Described is a configuration to remove false paths from an emulation netlist in a chip design under test (DUT). The configuration identifies, in an original netlist, an original subgraph of original logic gates, a subset of inputs (TI), and a subset of outputs (TO). The configuration generates a replicated subgraph of the original subgraph, the replicated subgraph having replicated logic gates corresponding to the original logic gates. The configuration connects the TI with a first replicated logic gate to a constant propagation source and remaining inputs of the replicated logic gates with corresponding original logic gates in the original netlist. The configuration disconnects, in the original netlist, output loads of TO, and connects the output loads of TO with a corresponding equivalent TO in the replicated subgraph. The configuration deletes, in the original netlist, original logic gates unconnected with an output load for TO in the original netlist.

Abstract: A system and method for mitigating memory transaction conflicts by receiving a first memory transaction from a first processor slice of a processor and a second memory transaction from a second processor slice of the processor. Further, one or more control signals are generated for the first memory transaction and the second memory transaction based on a determination that the first memory transaction and the second memory transaction have a target address associated with a first memory bank of a memory. The first memory transaction is selected to output to the first memory bank based on the one or more control signals.

Abstract: A check-out request for a license may be received from an application, e.g., an electronic design automation (EDA) application, and may be routed to a license server. The license may be granted to the application, where granting the license to the application may include establishing a connection between the license server and the application. A check-in request may be received for the license from the application. The license may be revoked, which may include terminating the connection between the license server and the application. A usage amount may be determined based on information about the check-out request and information about the check-in request.

Abstract: Merging store instructions for a memory includes receiving a first store instruction having a first address, and determining a first pattern based on a comparison of the first address and a second address of an entry within a buffer. Further, a size field of the entry is updated based on the first pattern. The first address of the first store instruction is merged with the second address within the entry to generate a merged instruction. The merged store instruction is communicated to the memory.

Abstract: A configuration may identify an IC chip component the IC chip component comprising one of a logic block, a memory block, and a power grid. A configuration may train a machine learning model based on one or more features and one or more labels corresponding to the identified IC chip component. A configuration may generate an artificial intelligence model having characteristics comprising the trained machine learning model, the one or more features, and the one or more labels. A configuration may generate a prediction for the one or more labels based on past, present and projected one or more features. A configuration may monitor future label prediction versus a failure threshold. A configuration may generate a notification in response to the failure threshold being reached.

Abstract: A system and method service memory transaction requests by receiving a memory transaction request for a first memory line from a first processor core of processor cores of a processing system. A second processor core of the processor cores is determined to include the first memory line in a shared state. Data of the first memory line is communicated from the second processor core to the first processor core based on determining that the second processor core comprises the first memory line in a shared state.

Abstract: A system uses machine learning models, such as neural networks for generating mask design from a circuit design. The machine learning models have inputs and outputs which are localized to a small region of the circuit design. The machine learning model takes as input features describing the circuit design in the neighborhood of a location and generates an offset distance as output. The system uses the offset distance to generate features of the mask design, for example, main features or assist features corresponding to a circuit design polygon. The system may use the offset distance for target optimization by modifying the circuit design polygon to obtain a circuit design polygon that has improved manufacturability.

Abstract: A method for generating a circuit layout includes generating a plurality of symbols. Each of the plurality of symbols identifies one of multiple versions of code describing a circuit layout. The method also includes loading the plurality of symbols into a design platform used to compile the code describing the circuit layout. The design platform has evaluators for the multiple versions of the code. The method further includes generating the circuit layout described by the code using the design platform.

Abstract: The present disclosure describes systems and methods for forming scan chains. The system includes a memory and a processor communicatively coupled to the memory. The processor receives a circuit design that includes a plurality of scan cells. The plurality of scan cells includes a first scan cell and a first set of scan cells coupled logically to the first scan cell. The processor forms the plurality of scan cells into a first scan chain such that the first set of scan cells are placed outside an extended neighborhood of the first scan cell. The extended neighborhood of the first scan cell includes (i) scan cells that are downstream of the first scan cell in the first scan chain and (ii) a scan cell that is adjacent to and upstream of the first scan cell in the first scan chain.

Abstract: Systems and methods for address mapping for a memory system are described. A system address that includes a first set of bits may be received. The first set of bits may be partitioned into at least a second set of bits and a third set of bits. A fourth set of bits may be determined based on the second set of bits. A memory address may be determined by using the third set of bits and the fourth set of bits.

Abstract: A request may be received to use a software on a first project. A first set of values may be extracted for a set of features of the first project. A classifier may be used to classify the first project based on the first set of values. It may be determined whether to grant the request to use the software on the first project based on an output of the classifier.

Abstract: Embodiments provide for improved placement bounds. An example method includes identifying, based on a first synthesizing of an integrated circuit layout representation, a plurality of integrated circuit endpoints. The example method further includes identifying, based on a plurality of feature vectors each representing an endpoint of the plurality of integrated circuit endpoints, a plurality of integrated circuit clusters. Each integrated circuit cluster comprises a unique subset of integrated circuit endpoints of the plurality of integrated circuit endpoints. The example method further includes applying, using a processor and based on a subsequent synthesizing of the integrated circuit layout representation, placement bounds to the integrated circuit layout representation. The placement bounds are applied based on the plurality of integrated circuit clusters.

Abstract: A system and method generates test patterns for simulating a circuit design. Generating the test patterns includes determining clock data of the circuit design. The clock data is determined by determining a first clock signal pair from clock signals, and determining a disturb cell based on the first clock signal pair. The disturb cell is electrically coupled to a first clock signal of the first clock signal pair, and to a second cell. The second cell is electrically coupled to a second clock signal of the first clock signal pair, and an input of the second cell is electrically coupled to an output of the disturb cell. A first test pattern is generated based on the clock data and is output to a memory to be used in simulating a circuit design.

Abstract: Certain aspects are directed to apparatus and methods for signal integrity monitoring. The method generally includes: receiving a data signal; generating a first set of delayed versions of the data signal via a plurality of delay elements; comparing each of the first set of delayed versions of the data signal with a clock signal; and generating an output signal based on the comparison.

Abstract: This disclosure describes a method for finding equivalent classes of hard defects in a stacked MOSFET array. The method includes identifying the stacked MOSFET array in a circuit netlist. The stacked MOSFET array includes standard MOSFETs sharing gate and bulk terminals. The method further includes determining electrical defects for the standard MOSFETs, grouping the electrical defects into at least one intermediate equivalent defect class based on a topological equivalence of the electrical defects, grouping the electrical defects in the at least one intermediate equivalent defect class into at least one final equivalent defect class based on an electrical equivalence of the electrical defects, performing a defect simulation on an electrical defect in the at least one final equivalent defect class, and attributing a result of the defect simulation on the electrical defect to additional electrical defects in the final equivalent defect class.

Abstract: A memory device includes bitcells connected to wordlines and bitlines, and driver circuitry that updates the bitcells. The driver circuitry includes first transistors, and a first inverter device. The first transistors drive a bitcell of a memory device. The first inverter device is coupled to the first transistors, and drives the first transistors with a first control signal. The first inverter device includes first inverter circuitry and second inverter circuitry. The first inverter circuitry receives a first signal, a first voltage, and a second voltage differing from the first voltage, and generates a first inverted signal based on the first signal, the first voltage and the second voltage. The second inverter circuitry receives the first inverted signal, the second voltage and a third voltage differing from the second voltage, and generates the first control signal based on the first inverted signal, the third voltage and the second voltage.