Abstract: For phase-shifting micro lithography, a method of assigning phase to a set of shifter polygons in a mask layer separated by a set of target features includes assigning a first phase to a first shifter polygon, identifying a set of target features that touch the first shifter polygon, and assigning a second phase to all shifter polygons in the set that touch the set of target features in contact with the first shifter polygon. The set of shifter polygons and the set of target features are separated into aggregates that are spatially isolated from each other such that the phase assignment in one aggregate does not affect the phase assignments in other aggregates.
Abstract: A method and an apparatus for constructing a model of a digital circuit which contains level sensitive latches. The model allows for time borrowing amongst latches. Chains of latches or latch paths are collapsed together. The resulting model can be used for simulation or synthesis.
Abstract: A hardware interface generates and synchronizes precisely timed digital signals. The hardware interface receives data bits and associated timing information for application to a Hardware Modeling Element (HME). Preferably there are at least two modules, each including a clock generating circuit which has an input for receiving a master clock signal, a divider circuit for generating therefrom a plurality of evenly timed internal clock signals, wherein a first one of the internal clock signals rises at the same time as the master clock signal, and a phase adjusting circuit for receiving a feedback control signal for adjusting a phase delay in accordance with a sensed throughput delay. Each module also includes a timing multiplexer which receives the internal clock signals and each having a plurality of data channels, each having approximately the same throughput delay.
Type:
Grant
Filed:
April 13, 1995
Date of Patent:
September 30, 1997
Assignee:
Synopsis, Incorporated
Inventors:
Andrew J. Read, Sani El-Fishawy, Robert Mardjuki, Michael Lee