Patents Assigned to Synopsys, Incorporated
  • Extracting accurate and efficient timing models of latch-based designs
    Patent number: 5790830
    Abstract: A method and an apparatus for constructing a model of a digital circuit which contains level sensitive latches. The model allows for time borrowing amongst latches. Chains of latches or latch paths are collapsed together. The resulting model can be used for simulation or synthesis.
    Type: Grant
    Filed: December 29, 1995
    Date of Patent: August 4, 1998
    Assignee: Synopsys, Incorporated
    Inventor: Russell B. Segal