Patents Assigned to Synopsys Taiwan Co., LTD.
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Patent number: 9311441Abstract: A designer uses an option device to switch one or more signal flows in a schematic design to create different versions for the same design. Currently, there is no related automatic tool for the automatic placement of option devices. In various embodiments, option device instances are used to decide option device positions. Option devices can be automatically placed and routing considered and adjusted as needed.Type: GrantFiled: November 14, 2014Date of Patent: April 12, 2016Assignee: Synopsys Taiwan Co., Ltd.Inventors: Jui-Hsiang Liu, Hsin-I Lin, Tung-Chieh Chen
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Patent number: 9305127Abstract: In one or more embodiments, a caching apparatus includes functionality to persist evaluation results associated with pcells in a design across sessions of an EDA application as well as across design libraries. The caching apparatus may create and maintain a mirror cache in a design library with only subMasters referenced by the design library. The contents of a central cache file or a mirror cache in the design library are examined for an evaluation result. If the evaluation result is not found in the central cache file, the evaluation result may be retrieved from the mirror cache if present.Type: GrantFiled: November 14, 2014Date of Patent: April 5, 2016Assignee: Synopsys Taiwan Co., Ltd.Inventors: Wei-Cheng Chen, Jen-Feng Huang
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Patent number: 9286433Abstract: A computer implemented method for forming an integrated circuit (IC) layout is presented. The method includes forming a constraint tree when a computer is invoked to receive a first layout of the IC and generating a second layout of the IC in accordance with the constraint tree.Type: GrantFiled: November 18, 2013Date of Patent: March 15, 2016Assignees: Synopsys Taiwan Co., Ltd., Synopsys, Inc.Inventors: Tung-Chieh Chen, Hung-Ming Chen, Yi-Peng Weng
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Patent number: 9256706Abstract: A computer-implemented method for generating a layout of a design includes invoking the computer to receive a schematic representation of the design, generating a connection graph associated with the design, comparing the connection graph with a plurality of connection graphs stored in a database and selecting a layout associated with the matching connection graph in generating the layout of the design.Type: GrantFiled: September 3, 2014Date of Patent: February 9, 2016Assignee: Synopsys Taiwan Co., Ltd.Inventors: Tung-Chieh Chen, Po-Hsun Wu, Po-Hung Lin, Tsung-Yi Ho
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Publication number: 20150294055Abstract: User's register transfer level (RTL) design is analyzed and instrumented so that signals of interest are preserved and can be located in the netlist after synthesis. Then, the user's original flow of RTL synthesis and design partition is performed. The output is analyzed to locate the signals of interest. Latches are selectively inserted to the netlist to ensure that signal values can be accessed at runtime. After that, a place and route (P&R) process is performed, and the outputs are analyzed to correlate signal names to registers (flip-flops and latches) or memory blocks locations is field programmable gate array (FPGA) devices. A correlation database is built and kept for runtime use. During runtime, a software component may be provided on a workstation for the user to query signal values corresponding to RTL hierarchical signal names.Type: ApplicationFiled: April 15, 2014Publication date: October 15, 2015Applicants: Synopsys, Inc., Synopsys Taiwan Co., Ltd.Inventors: Hung Chun Chiu, Meng-Chyi Lin, Kuen-Yang Tsai, Sweyyan Shei, Hwa Mao, Yingtsai Chang
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Patent number: 9081924Abstract: Methods and apparatus for recording and visualizing transactions of a test bench simulation are disclosed. Transaction-specific data generated from a test bench simulation may be displayed in a sequence diagram view to provide a view of the transactions arranged sequentially in time.Type: GrantFiled: March 14, 2011Date of Patent: July 14, 2015Assignees: Synopsys, Inc., Synopsys Taiwan Co., Ltd.Inventors: Yung Chuan Chen, I-Liang Lin, Li-Chi Chang, Bindesh Patel
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Patent number: 9053264Abstract: What-if simulation methods and systems are provided. A design coding in HDL (Hardware Description Language) and a simulation result corresponding to the design are provided. A what-if design scope and a what-if time window are received. A portion of the design is extracted from the design according to the what-if design scope, and primary input signals are determined during the extraction of the sub-design. Then, what-if simulation data is extracted from the simulation result according to the primary input signals and the what-if time window. A what-if test bench is generated according to the what-if simulation data, wherein the what-if simulation data is read, and the signal values are fed to a simulator according to the what-if test bench.Type: GrantFiled: October 7, 2011Date of Patent: June 9, 2015Assignees: Synopsys, Inc., Synopsys Taiwan Co., Ltd.Inventors: Chia-Chih Yen, Che-Hua Shih, Chun-Chi Lin
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Patent number: 9003350Abstract: A computer implemented method for routing a net includes selecting, using one or more computer systems, a first spine routing track from a first multitude of routing tracks in accordance with a first cost function, and further in accordance with data associated with the net and the first multitude of routing tracks. The method further includes generating, using one or more computer systems, a first spine wire on the selected first spine routing track.Type: GrantFiled: October 1, 2013Date of Patent: April 7, 2015Assignees: Synopsys Taiwan Co., Ltd., Synopsys, Inc.Inventors: Fong-Yuan Chang, Wei-Shun Chuang, Sheng-Hsiung Chen, Hsian-Ho Chang, Ruey-Shi Rau
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Patent number: 8990756Abstract: A computer-implemented method for routing at least one conductor includes generating the at least one conductor within a bounded region on a planar surface in accordance with a template, and placing at least one slit in the conductor when the conductor overlaps a specified region of the bounded region in accordance with a specified pattern.Type: GrantFiled: November 21, 2013Date of Patent: March 24, 2015Assignee: Synopsys Taiwan Co., Ltd.Inventors: Hsin-Po Wang, Song Yuan, Hung-Shih Wang
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Patent number: 8959473Abstract: Multiple level spine routing is disclosed. In some embodiments, in response to receiving a specification of a plurality of nets and a specification of a set of routing tracks available for main spines, a main spine routing track is assigned to each of the plurality of nets based at least in part on a cost function and main spine wires are generated on the assigned main spine routing tracks for each of the plurality of nets.Type: GrantFiled: November 4, 2011Date of Patent: February 17, 2015Assignees: Synopsys Taiwan Co., Ltd., Synopsys, Inc.Inventors: Fong-Yuan Chang, Wei-Shun Chuang, Sheng-Hsiung Chen, Hsian-Ho Chang, Ruey-Shi Rau
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Patent number: 8943452Abstract: A computer-implemented method for debugging the power aspect of an IC design by integrating the power specification expressed in certain power specification format and its corresponding circuit design within a power schematic diagram called power map. Power map is created by using a power data base generated by regrouping the original circuit design hierarchy to new hierarchies defined by the power specification. Power map contains power cell symbols (such as isolation cells, level shifters, power switches) and signal nets, and can show the relationship between power domains. Power map can also display mismatches or errors between the power specification and the circuit design for those signals connecting the power domains. Furthermore, power map can be used in conjunction with simulation result.Type: GrantFiled: December 19, 2012Date of Patent: January 27, 2015Assignee: Synopsys Taiwan Co., Ltd.Inventors: Chih-Neng Hsu, I-Liang Lin, Wen-Chi Feng
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Patent number: 8924912Abstract: A computer-implemented method to debug testbench code of a testbench associated with a circuit design by recording a trace of call frames along with activities of the circuit design. By correlating and displaying the recorded trace of call frames, the method enables users to easily trace as execution history of subroutines executed by the testbench thereby to debug the testbench code. In addition, users can trace source code of the testbench code by using the recorded trace of call frames. Furthermore, users can debug the testbench code utilizing a virtual simulation, which is done by post-processing records of the virtual simulation stored in a database.Type: GrantFiled: July 30, 2013Date of Patent: December 30, 2014Assignees: Synopsys, Inc., Synopsys Taiwan Co., Ltd.Inventors: Chia-Ling Ho, Jian-Cheng Lin, Jencheng Wang
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Patent number: 8893069Abstract: A computer-implemented method is disclosed for layout pattern or layout constraint reuse by identifying sub-circuits with identical or similar schematic structure based on a topology comparison strategy. The selected sub-circuit is transformed into a topology representing the relative positions among the instances of the selected sub-circuit. Based on the topology, one or more sub-circuits with identical or similar topologies in a predefined scope of a schematic are recognized and identified. Accordingly, the layout or the layout constraint of the selected sub-circuit is copied and associated to each of the identified sub-circuits. Furthermore, once the sub-circuits are identified, they can be listed on a user interface with notations to allow users to confirm each of the identified sub-circuits respectively.Type: GrantFiled: October 6, 2012Date of Patent: November 18, 2014Assignees: Synopsys, Inc., Synopsys Taiwan Co., Ltd.Inventors: Yu-Chi Su, Ming-I Lai, Hsiao-Tzu Lu
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Patent number: 8875081Abstract: A method for designing and making an integrated circuit is described. That method utilizes statistical models of wire segments to accurately estimate the expected length of minimum-length, orthogonal wire segments within a block. From these estimates, the method accurately estimates an ratio between the horizontal and vertical routing resources required, termed the “H/V Demand Ratio.” From the H/V Demand Ratio, an accurate estimate of the height and width of the block may be determined. Thereafter, placement and routing may be performed quickly and accurately, thereby allowing the block to be designed and manufactured quickly and cost effectively. A method for designing an integrated circuit with efficient metal-1 resource utilization is also described.Type: GrantFiled: February 26, 2013Date of Patent: October 28, 2014Assignees: Synopsys Taiwan Co., Ltd., Synopsys, Inc.Inventors: Fong-Yuan Chang, Sheng-Hsiung Chen, Tung-Chieh Chen, Ren-Song Tsay, Wai-Kei Mak
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Patent number: 8869084Abstract: A method for generating a layout for a cell of an integrated circuit (IC) guided by design rule checking (DRC) is disclosed. In the method, a model is defined, wherein the model comprises a plurality of parameters for generating a layout of the cell. Next an initial layout for the cell can be generated according to an initial set of values for the plurality of parameters. Then design rule checking (DRC) is performed for the initial layout based on a set of design rules. If any violations are found, the corresponding violation reports will be associated with the model. Therefore, a new set of values for the plurality of parameters can be generated by analyzing the violation reports collectively based on the model. With the new set of values for the plurality of parameters and above steps repeated, until no violation is found, a “DRC clean” layout can be generated.Type: GrantFiled: November 24, 2012Date of Patent: October 21, 2014Assignees: Synopsys, Inc., Synopsys Taiwan Co., Ltd.Inventors: Chien-Fu Chung, Yuan-Kai Pei, Shyh-An Tang
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Patent number: 8839179Abstract: A test system for testing prototype designs includes a host workstation, multiple interface devices, and multiple prototype boards. The prototype boards include programmable devices which implement one or more partitions of a user design and an associated verification modules. The verification modules probe signals of the partitions and transmit the probed signals to the interface devices. The verification modules can also transmit output signals generated by one or more partitions on the prototype boards to the host workstation via the interface devices, and transmit input signals, which are received from the host workstation via the interface devices, to one or more partitions on the prototype boards.Type: GrantFiled: April 3, 2013Date of Patent: September 16, 2014Assignee: Synopsys Taiwan Co., Ltd.Inventors: Yingtsai Chang, Sweyyan Shei, Hung-Chun Chiu, Meng-Chyi Lin, Hwa Mao, Ming Yang Wang, Yuchin Hsu
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Patent number: 8832615Abstract: A method for detecting anomalies in signal behaviors in a simulation of a low power IC includes receiving a circuit design and a power specification of the IC, determining at least one power sequence checking rule from the power specification, simulating the circuit design and the power specification to obtain a dump file, identifying at least one anomaly of the at least one power sequence checking rule based on the dump file, and generating information relevant to the identified anomaly of the at least one power sequence checking rule. The method further includes setting up a context in a debugger for debugging the anomaly by displaying a waveform of misbehaved signals associated with the anomaly in a waveform window, and a portion of the circuit design and/or a portion of the power specification associated with the anomaly in a text window.Type: GrantFiled: May 9, 2013Date of Patent: September 9, 2014Assignees: Synopsys, Inc., Synopsys Taiwan Co., Ltd.Inventors: Ming Han Hsieh, Chih-Neng Hsu, Ming-Hui Hsieh
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Patent number: 8832632Abstract: Techniques for compacting routing in lower level blocks to free routing resources for upper level blocks are disclosed. In some embodiments, a specification of a hierarchical integrated circuit design comprising a lower level block and an upper level block is obtained. The specification includes an initial routing plan for the lower level block. Subsequently, a compacted routing plan for the lower level block using constrained routing resources comprising fewer routing tracks than the initial routing plan and resulting in at least one unused track as well as a routing plan for the upper level block using the at least one unused track are generated.Type: GrantFiled: October 25, 2012Date of Patent: September 9, 2014Assignees: Synopsys Taiwan Co., Ltd., Synopsys, Inc.Inventors: Fong-Yuan Chang, Sheng-Hsiung Chen
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Patent number: 8789008Abstract: Methods for generating a device layout are provided. First, design rules corresponding to a specific technology are received. A selection of at least one element and a parameter value corresponding to at least one parameter on the selected element are received. A draft device layout corresponding to the selected element is generated by a device generator by referencing the parameter value and the design rules. A script is then executed to modify the draft device layout to generate an updated device layout. The script includes at least one command, and when the script is executed, the at least one command is performed to modify the parameter value of the at least one parameter of the selected element and cause the device generator to delete the old draft device layout and generate a new draft device layout by referencing the modified parameter value and the design rules.Type: GrantFiled: July 22, 2011Date of Patent: July 22, 2014Assignees: Synopsys Taiwan Co., Ltd., Synopsys, Inc.Inventors: Chih-Hung Chen, Wen-Hao Yu, Shyh-An Tang
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Patent number: 8782588Abstract: A computer implemented method for routing a net includes generating, using one or more computer systems, a first wire associated with the net in accordance with data associated with the net including a multitude of pins and partitioning, using the one or more computer systems, the multitude of pins into at least a first group of pins in accordance with a first cost function. The method further includes connecting, using the one or more computer systems, a second wire associated with the first group of pins to the first wire, and connecting, using the one or more computer systems, a third wire from a pin of the first group of pins to the second wire.Type: GrantFiled: October 1, 2013Date of Patent: July 15, 2014Assignees: Synopsys Taiwan Co., Ltd., Synopsys, Inc.Inventors: Fong-Yuan Chang, Wei-Shun Chuang, Sheng-Hsiung Chen, Hsian-Ho Chang, Ruey-Shi Rau