Patents Assigned to Synplicity, Inc.
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Patent number: 7107570Abstract: A method and system for user-defined triggering logic in a hardware description language is described. The method includes reading a file containing user-defined triggering logic described in a hardware description language (HDL), inserting and connecting the triggering logic to a circuit described in HDL, and compiling the HDL description of the circuit to generate a register transfer level (RTL) netlist.Type: GrantFiled: April 8, 2004Date of Patent: September 12, 2006Assignee: Synplicity, Inc.Inventors: Mario Larouche, Chun Kit Ng
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Patent number: 7093204Abstract: Methods and apparatuses to automatically generate time multiplexed multi-channel circuits from single-channel circuits. At least one embodiment of the present invention automatically and efficiently synthesize multi-channel hardware for time-multiplexed resource sharing by automatically generating a time multiplexed design of multi-channel circuits from the design of a single-channel circuit. Channel specific elements of the single-channel design (e.g., registers and memories) are replaced with corresponding elements of N-times more capacity for pipelining the signal processing for multiple channels.Type: GrantFiled: April 4, 2003Date of Patent: August 15, 2006Assignee: Synplicity, Inc.Inventors: Levent Oktem, Kenneth S. McElvain
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Patent number: 7082582Abstract: One embodiment of the present invention includes a technique for a gated clock conversion for a circuit which includes a gating circuit and a sequential element. The gating circuit has a gated clock net that drives a clock input of the sequential element. The sequential element receives a first input net at a data input and generates an output net. The gating circuit has a user-defined clock net. The technique includes determining the gating circuit and transforming the gating circuit to provide a second input net to the sequential element based on a cofactor condition of the gating circuit.Type: GrantFiled: August 13, 2003Date of Patent: July 25, 2006Assignee: Synplicity, Inc.Inventors: Drazen Borkovic, Kenneth S. McElvain
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Patent number: 7072818Abstract: Techniques and systems for debugging an electronic system having instrumentation circuitry included therein are disclosed. The techniques and systems facilitate analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the invention enables the hardware designs within the integrated circuit products to be comprehensively analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs.Type: GrantFiled: November 28, 2000Date of Patent: July 4, 2006Assignee: Synplicity, Inc.Inventors: John Mark Beardslee, Nils Endric Schubert, Douglas L. Perry
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Patent number: 7069526Abstract: Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the techniques and systems enable the hardware designs within the integrated circuit products to be comprehensively analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs.Type: GrantFiled: December 29, 2004Date of Patent: June 27, 2006Assignee: Synplicity, Inc.Inventors: Nils Endric Schubert, John Mark Beardslee, Douglas L. Perry
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Patent number: 7065481Abstract: Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the techniques and systems enable the hardware designs within the integrated circuit products to be comprehensively analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs.Type: GrantFiled: July 31, 2002Date of Patent: June 20, 2006Assignee: Synplicity, Inc.Inventors: Nils Endric Schubert, John Mark Beardslee, Gernot Heinrich Koch, Olaf Poeppe
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Patent number: 7051296Abstract: An apparatus having two or more parallel carry chain structures, each of the carry chain structures comprising a series of logical structures, where at least one of the logical structures within each of the carry chain structures has an associated input node, output node and carry node. The input node corresponds to a function input term, the output node corresponds to an output term of the function and the carry node corresponds to a carry value to a following logical structure in the series of logical structures.Type: GrantFiled: April 2, 2004Date of Patent: May 23, 2006Assignee: Synplicity, Inc.Inventor: Ken S. McElvain
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Patent number: 7010769Abstract: Methods and apparatuses for designing an integrated circuit. In one example of a method, a hardware description language (HDL) code is compiled to produce a technology independent RTL (register transfer level) netlist. A portion of an area of the IC is allocated to a specific portion of the technology independent RTL netlist. In a typical implementation of this method, the allocation restricts circuitry created from the specific portion to the portion of the IC.Type: GrantFiled: December 5, 2002Date of Patent: March 7, 2006Assignee: Synplicity, Inc.Inventors: Kenneth S. McElvain, Robert Erickson
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Method and apparatus for the design and analysis of digital circuits with time division multiplexing
Patent number: 7007254Abstract: Methods and apparatuses to design and analyze digital circuits with time division multiplexing. At least one embodiment of the present invention efficiently models subsystems connected by a TDM channel by introducing equivalent delays in the connections for the subsystems, where the delays are determined according to the upper bounds of the delays caused by the TDM channel. The TDM channel is modeled with its equivalent delays. Thus, a transformation tool is allowed to take into account the original constraints and time budgeting of the sending subsystem and the receiving subsystem. The problem of asynchronous clock domains is eliminated; and, simulation time of the multiplexed circuit is also improved. In some embodiments of the present invention, multiple TDM slots are assigned to a particular signal to reduce the equivalent connection delay caused by the TDM channel for the particular signal.Type: GrantFiled: January 17, 2003Date of Patent: February 28, 2006Assignee: Synplicity, Inc.Inventors: Drazen Borkovic, Kenneth S. McElvain -
Patent number: 6978430Abstract: Methods and apparatuses for designing a plurality of integrated circuits (ICs) from a language representation of hardware. In one example of a method, a technology independent RTL (register transfer level) netlist is partitioned between representations of a plurality of ICs. In a typical example of the method, a hardware description language (HDL) code is written and compiled without regard to splitting the design among multiple ICs. After compilation, a partition of the technology independent RTL netlist, obtained from the compilation, is performed among the multiple ICs. After a partition, the technology independent RTL netlist is mapped to a particular target technology (e.g. a particular IC vendor's architecture for implementing logic circuitry), and place and route tools may be used to create the design in multiple ICs (e.g. field programmable gate arrays).Type: GrantFiled: December 8, 2003Date of Patent: December 20, 2005Assignee: Synplicity, Inc.Inventors: Kenneth S. McElvain, Robert Erickson
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Patent number: 6973632Abstract: Methods and apparatuses to estimate delay for logic circuit optimization using back annotated placement and delay data. In one aspect of the invention, a method to design a logic circuit, the method includes: modifying a first path that is back annotated with first placement information and first delay information to generate a second path; and calculating a signal delay on the second path from second placement information for the second path, the first placement information and the first delay information (or, computing an adjustment to the first delay information from second placement information for the second path and the first placement information). In one example according to this aspect, the first placement information and the first delay information are back annotated from a timing analysis based on placing and routing at least the first path. An actual route is determined from the first placement information in calculating the signal delay.Type: GrantFiled: December 4, 2002Date of Patent: December 6, 2005Assignee: Synplicity, Inc.Inventors: Dhananjay S. Brahme, Jovanka Ciric, Kenneth S. McElvain
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Patent number: 6934183Abstract: A resetable memory is described that includes a memory without reset capability having a data output coupled to a first input of a first multiplexer. A second input of the first multiplexer has a reset value input. A channel select for the first multiplexer is coupled to a resetable storage cell output that indicates whether a storage cell within the memory without reset capability has been written to after a reset or has not been written to after a reset.Type: GrantFiled: March 18, 2004Date of Patent: August 23, 2005Assignee: Synplicity, Inc.Inventors: Vijay K. Seshadri, Kenneth S. McElvain
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Patent number: 6931572Abstract: Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. In particular, the techniques and systems relate to design instrumentation circuitry that facilitates the analysis, diagnosis and debugging of the hardware designs. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the techniques and systems enable the hardware designs within the integrated circuit products to be comprehensively analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs.Type: GrantFiled: November 28, 2000Date of Patent: August 16, 2005Assignee: Synplicity, Inc.Inventors: Nils Endric Schubert, John Mark Beardslee, Douglas L. Perry
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Patent number: 6904577Abstract: Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the techniques and systems enable the hardware designs within the integrated circuit products to be comprehensively analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs.Type: GrantFiled: April 2, 2003Date of Patent: June 7, 2005Assignee: Synplicity, Inc.Inventors: Nils Endric Schubert, John Mark Beardslee, Douglas L. Perry
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Patent number: 6904576Abstract: A method and apparatus is provided to debug using replicated logic. A text representation of a circuit is compiled to generate a first register transfer level (RTL) netlist. The netlist may be mapped to a target architecture, such as a field programmable gate array (FPGA). The netlist may be used to program an FPGA to create a prototype board for debugging. After debug, a portion of the circuit that a designer would like to analyze is selected. The selected portion of the circuit is replicated. Delay logic is inserted to delay the inputs into the replicated portion of the circuit. The text representation of the circuit is recompiled to generate a second RTL netlist. The second RTL netlist may be mapped to a target architecture, such as a FPGA or application specific integrated circuit (ASIC).Type: GrantFiled: August 9, 2002Date of Patent: June 7, 2005Assignee: Synplicity, Inc.Inventors: Chun Kit Ng, Kenneth S. McElvain
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Patent number: 6836420Abstract: A resetable memory is described that includes a memory without reset capability having a data output coupled to a first input of a first multiplexer. A second input of the first multiplexer has a reset value input. A channel select for the first multiplexer is coupled to a resetable storage cell output that indicates whether a storage cell within the memory without reset capability has been written to after a reset or has not been written to after a reset.Type: GrantFiled: March 4, 2002Date of Patent: December 28, 2004Assignee: Synplicity, Inc.Inventors: Vijay K. Seshadri, Kenneth S. McElvain
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Patent number: 6823497Abstract: Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the techniques and systems enable the hardware designs within the integrated circuit products to be comprehensively analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs.Type: GrantFiled: July 31, 2002Date of Patent: November 23, 2004Assignee: Synplicity, Inc.Inventors: Nils Endric Schubert, John Mark Beardslee, Gernot Heinrich Koch, Olaf Poeppe
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Patent number: 6807556Abstract: An apparatus having two or more parallel carry chain structures, each of the carry chain structures comprising a series of logical structures, where at least one of the logical structures within each of the carry chain structures has an associated input node, output node and carry node. The input node corresponds to a function input term, the output node corresponds to an output term of the function and the carry node corresponds to a carry value to a following logical structure in the series of logical structures.Type: GrantFiled: October 27, 2000Date of Patent: October 19, 2004Assignee: Synplicity, Inc.Inventor: Ken S. McElvain
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Patent number: 6734472Abstract: A power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device. An embodiment describes the routing of a shield mesh of both power and ground lines to remove noise created by capacitive and inductive coupling. Relatively long signal lines are routed in between fully connected power and ground shield mesh which may be generated by a router during the signal routing phase or during power mesh routing phase. Leaving only the odd tracks or the even tracks for signal routing, power mesh (VDD) and ground mesh (VSS) are routed and fully interconnected leaving shorter segments and thereby reducing the RC effect of the circuit device. Another embodiment presents a technique where the signals are shielded using the power and ground mesh for a gridless routing. Another embodiment presents a multi-layer grid routing technique where signals are routed on even grid and the power and ground lines are routed on odd grid.Type: GrantFiled: April 25, 2002Date of Patent: May 11, 2004Assignee: Synplicity, Inc.Inventor: Iu-Meng Tom Ho
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Patent number: 6735743Abstract: A method is described that comprises determining a state machine design point from a plurality of state machine design point options. At least one of the plurality of state machine design point options corresponds to a safe design point. The method then further comprises, if the safe design point is the determined state machine design point, forming a safe state machine model. The safe state machine model has valid state logic separated from invalid state logic. Another method is described that comprises detecting an invalid state of a state machine with invalid state logic and setting a state machine register to a valid state with the invalid state logic. The method then further comprises continuing valid state operation of the state machine with valid state logic. The valid state logic is separated from the invalid state logic.Type: GrantFiled: April 5, 2001Date of Patent: May 11, 2004Assignee: Synplicity, Inc.Inventor: Kenneth S. McElvain