Abstract: Method and apparatus for processing data packets within a communication system such as a synchronous optical network (SONET) detect an invalid byte and drop and shift bytes of data to address an invalid byte. A method according to one embodiment of the present invention, includes receiving a first data packet in the communication system. Thereafter, it is determined whether this packet ends with both a valid byte and an invalid byte of data. If both the valid and invalid bytes are present, the invalid byte is dropped and a valid byte from a succeeding data packet is concatenated with the valid byte of the first data packet, and byte shifting occurs in the succeeding data packet. Byte shifting continues until a second packet ending with an invalid byte is encountered. Skipping a clock cycle at the end of the second packet with the invalid byte results in packets with only valid data.

Abstract: A method and circuitry for detecting a pattern in received data such as the A1A2 boundary in a SONET frame after deserialization. Two consecutive pluralities of bytes of incoming data are stored and compared with the A1 and A2 values (or bit shifted versions of the A1 and A2 values) until the boundary is detected. The data are then bit shifted so that every byte on the bus is either A2 or A1. A new aligned data bus is then formed such that the last A1 bit occurs on the data bus for a given clock cycle and the first A2 bit occurs on the data bus during the next clock cycle.