Abstract: A self-calibrated system on a chip includes a semiconductor substrate, at least one silicon intellectual property (SIP) circuit including dynamic random access memories (DRAMs), a calibration circuit, and a function circuit, a cyclic oscillator, and a control circuit. Each DRAM has a coarsely-tuned capacitance value and a coarsely-tuned resistance value. The calibration circuit has a finely-tuned capacitance value and a finely-tuned resistance value. The cyclic oscillator transmits an oscillating clock signal to the control circuit to choose and provide the coarsely-tuned capacitance value, the coarsely-tuned resistance value, the finely-tuned capacitance value and the finely-tuned resistance value for the function circuit, thereby adjusting a function parameter.

Abstract: A system-on-chip module for avoiding redundant memory access is provided, comprising at least one microprocessor, a DRAM and a DRAM controller. The DRAM and the microprocessor are integrated and formed in the system-on-chip module commonly. The DRAM controller is electrically connected between the DRAM and the microprocessor, and includes at least one column cache unit such that each microprocessor is able to perform read or write command to the DRAM through its corresponding column cache unit. Compared with the prior arts, the present invention is beneficial to provide better data access quality, efficiency and lower cost and complexity of the system architecture. Thus, the present invention is believed to be applied widely and having greater industrial applicability.