Abstract: A circuit simulator for a semiconductor device with reduced channel length includes a method of calculating a model formula for circuit simulation of a semiconductor device; calculating first parasitic resistance independent of gate voltage using actually measured device data; calculating second parasitic resistance dependent on the gate voltage using I-V characteristic of the device without the first parasitic resistance; dividing the second parasitic resistance into channel resistance and third parasitic resistance generated under both ends of a gate length using plural kinds of diffusion resistance TEG in which the width W of each kind of diffusion resistance is the same as each other, but the length L of each kind of diffusion resistance is different from the other kinds of diffusion resistance; and obtaining an I-V characteristic formula for the semiconductor device using the third parasitic resistance as an independent characteristic.

Abstract: It is an object of the invention to obtain a model formula for a circuit simulator that can be applied to a semiconductor device in which a channel length thereof becomes further shorter. A method of calculating a model formula for circuit simulation of a semiconductor device is provided.