Abstract: A method for directly measuring the area of a topological surface with an arbitrary boundary shape lying in a fixed elevation different from a fixed surrounding surface elevation relies upon binocular stereo vision. Three stereo correlation measurements are made, one over a window entirely within the surface of interest, a second over a window outside the surface of interest and within the surrounding area, and a third over a window fully containing the surface of interest as well as some of the surrounding area. The correlation measured in the third case is the linear sum of the correlation value over each of the first two cases weighted by the proportion of the window that the two surfaces occupy.

Abstract: A system for shape recognition includes a spatial convolution filter which has an approximately band pass response. The filter is applied to a camera image and the sign of the filter's output is used to produce a second binary image. At sufficiently coarse (low center spatial frequency) scales, this image tends to change isolated shapes into single blob-shaped regions. The same convolution operator is then reapplied to this binary signal blob image and peaks in the output of the second convolution are used as the primitive elements for building a shape description. By processing the image with operators of two different scales the peaks shift position. The location of peaks from the coarse scale operator together with vectors to the fine scale peaks provide a description of the shape for a look-up table or other system.

Abstract: A system is disclosed which enables signals to be supplied at precisely desired times in an automatic test system. The apparatus includes a base delay memory which stores information representing the higher order bits of a time delay, while vernier memories store information relating to the lower order bits of the time delay. Offset memories enable storing calibration data. The base delay memory controls at least two counters in independent signal paths, while the vernier and offset memories control appropriate deskew units for further delaying the counter output signal as desired. The system enables sharing of resources, yet eliminates the need for repetitively loading correction data for deskew operations.

Abstract: Apparatus for delaying an electrical signal includes a sequence of stages, each for delaying the signal. A coarser stage delays the signal by multiples of a predetermined fundamental delay interval and a finer stage provides for fine adjustment of the delay. The fine stage includes an integral number N of delay elements, the total providing a delay interval greater than the fundamental delay interval, whereby the fine delay intervals compensate for fabrication tolerances to enable accurate calibration of the combined system by post-fabrication measurement. In one implementation each delay stage includes a tapped transmission line to provide delay intervals, in another a ramp generator is used.

Abstract: A multi-marker, multi-destination timing signal generator including a count-setting memory for storing a plurality of pulse-count values in a numerical order and a pulse counter for counting the number of pulses from a master clock. An output selection memory stores, for each pulse count value, enabling signals for a plurality of output elements so that a marker signal generated when the pulse counter equals a pulse-counter value in memory may be selectively routed to one or more output elements. The addresses of the count-setting memory and the output selection memory are maintained by an address counter. When the value of the pulse counter equals a pulse-count value stored in the count-setting memory, the address counter counts to the next address value for locating successive values in the count-settiong memory and the output selection memory.

Abstract: A high precision analog to digital converter comprises the combination of an imperfect or low resolution digital to analog converter having an error function known in terms of orthonormal components and an error compensating device capable of generating correction terms which do not interact with one another. The correction terms are based on orthonormal components namely, the Walsh function components, of each signal level to be compensated. At most only one weighting value per bit is required, the combination of which will compensate for errors of any bit combination. In a specific embodiment employing feedback compensation, the output of the low resolution converter and of the compensating device may be summed to produce a high performance, high precision converter with increased accuracy and resolution.

Abstract: A simulation system for visual signal processing circuits is presented which provides a detailed, pixel level analysis of the timing while actually performing the simulation at the frame level. Input to the circuit is the form of images captured by a video camera. The processing of a frame of image data by each circuit component is simulated and the resulting frames of image data are stored until they are no longer needed by other components. The output of the simulated circuit is displayed on a monitor.The timing of the circuit is analyzed for distinct groups of components which must operate in synchronism. Scaling factors are calculated for each net in the group from the incremental scaling rate of each component and the connectivity of the circuit. The scaling factors indicate the relative rate at which value pixels arrive at each net. The time at which a reference pixel arrives at each net is then computed to ensure that corresponding pixels arrive together at components with multiple inputs.

Abstract: An arithmetic logic system for performing a variety of arithmetic and logical functions on pixel input streams such as averaging down the input image stream, computation of absolute values, and signed or unsigned, clipped or unclipped, addition, subtraction and multiplication. The arithmetic logic system has a first arithmetic logic unit connected to a plurality of input signals. A second arithmetic logic unit is coupled to the first arithmetic logic unit and operates on the output of the first arithmetic logic unit. A control unit is coupled to the first and second arithmetic logic units and controls the operation of the second arithmetic logic unit based on the output of the first arithmetic logic unit.

Abstract: The present invention relates to a brick handling system for conveying brick slugs to and through a slug cutting device such as a wire bank cutter. More particularly, the system comprises an off bearing belt that conveys slugs to a discharge point where an over-hanging pusher-puller assembly acts to pull one slugs off said off bearing belt onto a slug support. After this a second slug is transferred to the discharge point such that said first and second slugs are horizontally aligned and disposed in side-by-side relationship. At this point, the same pusher-puller assembly is operative to engage said first slug on said slug support and push the same towards said second slug, engaging said second slug and continuing to transfer both first and second slugs across said conveyor towards the wire bank cutter.