Abstract: The invention relates to a method for configuring a memory with I/O support. The aim of the invention is to guarantee the processor and I/O functional units that function in time-critical conditions the appropriate priority for data access, using simple programs. To this end, an input memory area which the I/O unit can only write into and which the processor unit can only read out of and an output memory area which the I/O unit can only read out of and which the processor unit can only write into are specified in the processor.

Abstract: A method for controlling functional units in a processor, according to which in a configuration a sequence of primary instruction words which consists of several instruction word parts and originates from a translation of a program code is compressed and stored as a sequence of associated program words. The invention also relates to a processor system for carrying out this method. The aim of the invention is to increase operating speed in an application-specific manner while retaining a low program word width. To this end, as regards the method, a program word contains a first characteristic of a primary instruction word and instruction word parts which differentiate the primary instruction word belonging to the program word from the primary instruction word belonging to the characteristic.

Abstract: The invention relates to a method and an arrangement for instruction word generation in the controlling of functional units in a processor, the instruction words comprising a plurality of instruction word parts. In this case, in a program sequence, under the control of a program word, an instruction word is taken from a row—determined by a reading row number—of an instruction word memory that can be written to row by row, the said instruction word is altered by means of substitution of an instruction word part by the information part of the respective program word and is written back to a row of the instruction word memory, the said row being determined by a writing row number. Afterwards, an instruction word—which is generated in this way and is to be executed in accordance with the program—for controlling the functional units is output to the processor.

Abstract: Finite field multiplication of first and second Galois elements having n bit places and belonging to a Galois field GF 2n described by an irreducible polynomial is performed by forming an intermediate result Z of intermediate sums of partial products of bit width 2n?2 in an addition part of a Galois multiplier. The intermediate result Z is processed in a reduction part of a Galois multiplier by modulo dividing by the irreducible polynomial, whereby after all XOR's are traversed a result E with n bits is computed.

Abstract: In a data memory arrangement for a microprocessor system, in which the data memory is designed as a group memory composed of element memories in which data are storable in data groups having a plurality of elements under a group address in each instance, in order to make available a stack in which the memory space can be optimally utilized without the occurrence of memory gaps, the use is proposed of at least one memory pointer that has a group address component and an element address component. The stack memory can be operated with data words whose width is smaller than the data group width, without unutilized memory areas occurring in the stack.

Abstract: A data calculating device preferably used to improve the calculation precision when fixed-point calculation is performed by block-floating-point system. Each piece of data of a data group is calculated, the minimum scale factor representative of the calculated data is detected as a group scale factor (GSF), and calculated data is subjected to scaling based on the detected GSFs. These processing are applied to each data group of a data block. The minimum GSF out of the detected GSFs is detected as a block scale factor (BSF). When calculation of the calculated data is performed again, the calculated data of the data group is subjected to scaling according to the GSFs and BSF before the calculation performed again.

Abstract: A procedure and a processor arrangement for parallel data processing in which data are read out from a data memory and are conveyed via a communications unit to processing units for parallel processing. The data are divided into data groups with several elements and are stored in a group memory under a common address. To each data group, a processing unit is allocated, in that at least one element of a data group can be directly linked to the allocated processing unit, directly bypassing the communications unit. In a parallel fashion, a data group is read out from the data memory and is distributed over one or several processing units and is processed in a parallel fashion in the latter.

Abstract: The invention relates to a method for receiving spread-spectrum signals for fine time synchronization of correlators in a RAKE receiver. The objective of the invention is to produce a signal that is to be transmitted with the highest possible signal to noise ratio on the basis of the received signal. To achieve this, a higher level unit intervenes in the normal adjustment of a first basic time lag in a first RAKE finger and the normal adjustment of a second basic time lag in a second RAKE finger when the difference between the basic time lags of both RAKE fingers corresponds to a minimum level, and subsequently carries out a joint adjustment for both RAKE fingers, taking time error estimates for both RAKE fingers into account.