Abstract: Loudspeaker systems and assemblies are provided in which mid-frequency producing drivers are provided on opposing sides of a high frequency source comprising a linear high-frequency source connected to a waveguide. Crossover circuitry is provided such that the acoustic output from the mid-frequency drivers overlaps with that of the high-frequency source over an intermediate frequency range associated with acoustic interference between the mid-frequency producing drivers. In some embodiments, the mid-frequency producing drivers are recessed behind the output of the waveguide, and optionally angled outwardly from the waveguide, in order decrease the distance therebetween.

Abstract: A loudspeaker array element with an internal rigid structural frame and at least one interface for attaching one or more of enclosures, rigging components, waveguides, sound chambers, transducers and electronics to the frame is provided. Further configurations are provided for heat sinking of electrically powered devices such as loudspeakers, as well as power amplifiers, digital signal processing and networking hardware.

Abstract: A control and distribution system provides electrical power distribution, audio signal distribution, and control signal distribution to one or more audio components, such as a powered loudspeaker element or a signal conditioning device such as a rack-mounted amplifier. Embodiments allow for the monitoring and/or control of parameters and/or components at or near the endpoint of the system. These parameters or components include low-level parameters associated with the external audio devices, as opposed to merely higher level parameters of the system. The control and distribution system may include an uninterrupted power source for providing power in an online or offline mode to selected components of the external audio devices. In some embodiments, online backup power is provided to low-power components without providing power to amplifiers within the external audio devices.

Abstract: Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing group data handling operations that re-arrange data elements in different ways in response to data handling instructions, the execution unit further capable of executing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operates on the multiple data elements stored in registers in the register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results.

Abstract: A loudspeaker array element with an internal rigid structural frame and at least one interface for attaching one or more of enclosures, rigging components, waveguides, sound chambers, transducers and electronics to the frame is provided. Further configurations are provided for heat sinking of electrically powered devices such as loudspeakers, as well as power amplifiers, digital signal processing and networking hardware.

Abstract: A control and distribution system provides electrical power distribution, audio signal distribution, and control signal distribution to one or more audio components, such as a powered loudspeaker element or a signal conditioning device such as a rack-mounted amplifier. Embodiments allow for the monitoring and/or control of parameters and/or components at or near the endpoint of the system. These parameters or components include low-level parameters associated with the external audio devices, as opposed to merely higher level parameters of the system. The control and distribution system may include an uninterrupted power source for providing power in an online or offline mode to selected components of the external audio devices. In some embodiments, online backup power is provided to low-power components without providing power to amplifiers within the external audio devices.

Abstract: Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing group data handling operations that re-arrange data elements in different ways in response to data handling instructions, the execution unit further capable of executing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operates on the multiple data elements stored in registers in the register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results.

Abstract: Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing group data handling operations that re-arrange data elements in different ways in response to data handling instructions, the execution unit further capable of executing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operates on the multiple data elements stored in registers in the register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results.

Abstract: Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing group data handling operations that re-arrange data elements in different ways in response to data handling instructions, the execution unit further capable of executing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operates on the multiple data elements stored in registers in the register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results.

Abstract: A method for identifying and recording the relative positions of loudspeakers in an array with respect to one another using amplifiers connected on a network.

Abstract: A luminescence quantum efficiency measuring instrument is provided for easily and surely changing luminescence of a luminescent sample exhibiting strong luminescence anisotropy into an isotropic luminescence and for accurately measuring the luminescence quantum efficiency of the luminescent sample. The luminescence quantum efficiency measuring instrument comprises an integrating sphere (1) having a center, an excitation light entrance window (2), and a detection probe end (3) connected to a spectroscope, the excitation light entrance window and the detection probe end being disposed in respective directions perpendicular to each other on a plane including the center, wherein a luminescent sample (5) is disposed inside the integrating sphere (1) and on a vertical line extending from the center and vertical to the plane, and a baffle plate (7) is disposed at a place through which the luminescent sample (5) is seen from the detection probe end (3).

Abstract: The present invention provides a system and method for improving the performance of general-purpose processors by implementing a functional unit that computes the product of a matrix operand with a vector operand, producing a vector result. The functional unit fully utilizes the entire resources of a 128b by 128b multiplier regardless of the operand size, as the number of elements of the matrix and vector operands increase as operand size is reduced. The unit performs both fixed-point and floating-point multiplications and additions with the highest-possible intermediate accuracy with modest resources.

Abstract: A system and software for improving the performance of processors by incorporating an execution unit configurable to execute a plurality of instruction streams from the plurality of threads, wherein each instruction stream includes a group instruction that operates on a plurality of data elements in partitioned fields of at least one of the registers to produce a catenated result.

Abstract: A programmable processor and method for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying both a mask and a register containing data, the mask comprising fields that each correspond to a field of the data contained in the register, the execution unit is operable to detect some of the fields of the mask as having a predetermined value and identifying corresponding fields of the data contained in the register as write-enabled data fields; and cause the write-enabled data fields to be written to a specified memory location.

Abstract: A programmable processor and method for improving the performance of processors by incorporating an execution unit configurable to execute a plurality of instruction streams from the plurality of threads, wherein each instruction stream includes a group instruction that operates on a plurality of data elements in partitioned fields of at least one of the registers to produce a catenated result.

Abstract: A system and software for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying both a mask and a register containing data, the mask comprising fields that each correspond to a field of the data contained in the register, the execution unit is operable to detect some of the fields of the mask as having a predetermined value and identifying corresponding fields of the data contained in the register as write-enabled data fields; and cause the write-enabled data fields to be written to a specified memory location.

Abstract: A programmable processor and system for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying three registers each containing a plurality of data elements, the execution unit operable to multiply the first and second registers and add the third register to produce a catenated result containing a plurality of data elements. Additional instructions provide group floating-point subtract, add, multiply, set less, and set greater equal operations. The set less and set greater equal operations produce alternatively zero or an identity element for each element of a catenated result, the result facilitating alternative selection of individual data elements using bitwise Boolean operations and without requiring conditional branch operations.

Abstract: A programmable processor and method for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying a data selection operand and a first and a second register providing a plurality of data elements, the data selection operand comprising a plurality of fields each selecting one of the plurality of data elements, the execution unit operable to provide the data element selected by each field of the data selection operand to a predetermined position in a catenated result.

Abstract: A method and software for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying three registers each containing a plurality of data elements, the execution unit operable to multiply the first and second registers and add the third register to produce a catenated result containing a plurality of data elements. Additional instructions provide group floating-point subtract, add, multiply, set less, and set greater equal operations. The set less and set greater equal operations produce alternatively zero or an identity element for each element of a catenated result, the result facilitating alternative selection of individual data elements using bitwise Boolean operations and without requiring conditional branch operations.

Abstract: A programmable processor that comprises a general purpose processor architecture, capable of operation independent of another host processor, having a virtual memory addressing unit, an instruction path and a data path; an external interface; a cache operable to retain data communicated between the external interface and the data path; at least one register file configurable to receive and store data from the data path and to communicate the stored data to the data path; and a multi-precision execution unit coupled to the data path. The multi-precision execution unit is configurable to dynamically partition data received from the data path to account for an elemental width of the data and is capable of performing group floating-point operations on multiple operands in partitioned fields of operand registers and returning catenated results. In other embodiments the multi-precision execution unit is additionally configurable to execute group integer and/or group data handling operations.