Abstract: An exercise machine is disclosed. The exercise machine comprises a pancake motor. The exercise machine comprises a torque controller coupled to the pancake motor. The exercise machine comprises a high resolution encoder coupled to the pancake motor.

Abstract: Techniques in advanced deep learning provide improvements in one or more of accuracy, performance, energy efficiency, and cost. In a first embodiment, a scaled array of processing elements is implementable with varying dimensions of the processing elements to enable varying price/performance systems. In a second embodiment, an array of clusters communicates via high-speed serial channels. The array and the channels are implemented on a Printed Circuit Board (PCB). Each cluster comprises respective processing and memory elements. Each cluster is implemented via a plurality of 3D-stacked dice, 2.5D-stacked dice, or both in a Ball Grid Array (BGA). A processing portion of the cluster is implemented via one or more Processing Element (PE) dice of the stacked dice. A memory portion of the cluster is implemented via one or more High Bandwidth Memory (HBM) dice of the stacked dice.

Abstract: A concrete block includes first, second, third, fourth, fifth, and sixth planar faces.

Abstract: An antenna system includes a right-hand circularly polarized antenna for receiving Global Navigation Satellite System (GNSS) signals and located on a receiver housing; a vertical semitransparent screen for providing an Down/Up ratio DU 9 ? 0 = DU ? ( ? e = 9 ? 0 ? ) = F ? ( - 9 ? 0 ? ) F ? ( 9 ? 0 ? ) of ?13 dB or better for at least some GNSS frequencies; the semitransparent screen being connected to a ground plane of the antenna; the ground plane being connected to a conductive receiver housing; the semitransparent screen further comprising a horizontal slot to which sets of lumped impedance elements are connected. Each set includes several lumped elements; where the lumped elements are capacitors and/or inductors and/or resistors; where the lumped elements in each set are connected in parallel or series; and the semitransparent screen including at least 4 segments arranged symmetrically around the center of the antenna and connected to each other.

Abstract: Herein are disclosed computation units for batch normalization. A computation unit may include a first circuit to traverse a batch of input elements xi having a first format, to produce a mean ?1 in the first format and a mean ?2 in a second format, the second format having more bits than the first format. The computation unit may further include a second circuit operatively coupled to the first circuit to traverse the batch of input elements xi to produce a standard deviation ? for the batch using the mean ?1 in the first format. The computation unit may also include a third circuit operatively coupled to the second circuit to traverse the batch of input elements xi to produce a normalized set of values yi using the mean ?2 in the second format and the standard deviation ?.

Abstract: Techniques in advanced deep learning provide improvements in one or more of cost, accuracy, performance, and energy efficiency. The deep learning accelerator is implemented at least in part via wafer-scale integration. The wafer comprises a plurality of processor elements, each augmented with redundancy-enabling couplings. The redundancy-enabling couplings enable using redundant ones of the processor elements to replace defective ones of the processor elements. Defect information gathered at wafer test and/or in-situ, such as in a datacenter, is used to determine configuration information for the redundancy-enabling couplings.

Abstract: Described embodiments provide systems and methods for providing data loss prevention via an embedded browser. An interprocess communication (IPC) manager may interface with an embedded browser to control the transfer of data from a first application to a second application in accordance with a policy. The IPC manager may detect a command to store data accessed on the first application via the embedded browser and store the data onto a secure container. The secure container may be dedicated to the embedded browser. The IPC manager may subsequently detect a command to retrieve data from the secure container and to replicate the data onto the second application. The IPC manager may determine a policy to apply to the data. The policy may specify whether the data from the first application is permitted to be replicated onto the second application. The IPC manager may subsequently replicate the data on the second application.

Abstract: A device architecture includes a spatially reconfigurable array of processors, such as configurable units of a CGRA, having spare elements, and a parameter store on the device which stores parameters that tag one or more elements as unusable. Technologies are described which change the pattern of placement of configuration data, in dependence on the tagged elements. As a result, a spatially reconfigurable array having unusable elements can be repaired.

Abstract: A multi-input single output power system for outputting an output voltage on an output node. It includes a first integrated circuit (IC) converter device and a second IC converter device. The first IC converter device has a first pin to receive a first input voltage, a second pin to output the output voltage, and a first power unit coupled between the first pin and the second pin. The second IC converter device has a first pin to receive a second input voltage, a second pin to output the output voltage, a second power unit coupled between the first pin of the second IC converter device and the second pin of the second IC converter device, and a third pin. The third pin receives an external phase shedding control signal to determine whether to stop the second power unit from providing power to the output node.

Abstract: A patient control is disclosed that facilitates operation of an implantable medical device.

Abstract: An information processing apparatus includes: a storage that stores templates defining a display form of a ticker; a selection unit that selects a template stored in the storage; a material data acquisition unit that acquires material data to be displayed on the ticker; a production unit that produces ticker data by applying the template selected by the selection unit to the material data acquired by the material data acquisition unit; and a provision unit that provides provision data including the ticker data produced by the production unit.

Abstract: A functional unit for a data processor comprises an input register to store a variable X; a first circuit, having an input connected to the input register and an output, to generate a value eX on its output; a second circuit, having an input connected to the input register and an output, to generate an output which is a value (tan h(X/2)+1)/2 on its output; a comparator, having an input connected to the input register and an output, to generate a line on its output based on a comparison between X and a constant; and a selector to select between inputs connected to the outputs of the first circuit and the second circuit, in response to the output of the comparator, and provide an output representing a value sigmoid(X).

Abstract: A three-dimensional printing system includes a print engine, a storage subsystem, and a controller. The print engine includes a resin vessel having a lower side with a transparent sheet, a light engine that defines a build field above the transparent sheet, and a motorized carriage for holding a support tray with a lower surface above the resin vessel. The storage subsystem is configured to store support trays. The controller is configured to: receive a build order including a plurality of incoming files individually defining a three-dimensional article to be fabricated, process and determine breakage-related risk factors for the processed files, define a build plan for at least some of the plurality of processed files based at least partly upon the determined risk factors, and operate the print engine and the storage subsystem to build and store three-dimensional articles according to the defined build plan.

Abstract: The subject disclosure presents systems and methods for automatically selecting meaningful regions on a whole-slide image and performing quality control on the resulting collection of FOVs. Density maps may be generated quantifying the local density of detection results. The heat maps as well as combinations of maps (such as a local sum, ratio, etc.) may be provided as input into an automated FOV selection operation. The selection operation may select regions of each heat map that represent extreme and average representative regions, based on one or more rules. One or more rules may be defined in order to generate the list of candidate FOVs. The rules may generally be formulated such that FOVs chosen for quality control are the ones that require the most scrutiny and will benefit the most from an assessment by an expert observer.

Abstract: A method for selectively dropping out feature elements from a tensor is disclosed. The method includes generating a mask that has a plurality of mask elements. Each mask element includes a corresponding plurality of bits representing either a first value or a second value, to indicate whether a corresponding feature element of the tensor output by a neural network layer is to be dropped out or retained. Each mask element of the plurality of mask elements of the mask is compressed to generate a corresponding compressed mask element of a plurality of compressed mask elements of a compressed mask, thereby generating the compressed mask from the mask. Each compressed mask element of the plurality of compressed mask elements includes a corresponding single bit. Feature elements are selectively dropped from the tensor, based on the compressed mask.

Abstract: A computation unit computes a function f(I). The function f(I) has a target output range over a first domain of an input I encoded using a first format. A first circuit receives the encoded input I in the first format including X bits, to add an offset C to the encoded input I to generate an offset input SI=I+C, in a second format including fewer than X bits. The offset C is equal to a difference between the first domain in f(I) and a higher precision domain of the second format for the offset input SI. A second circuit is operatively coupled to receive the offset input SI in the second format, to output a value equal to a function f(SI) to provide an encoded output value f(I).

Abstract: Testability of memory on integrated circuits is improved by connecting storage elements like latches in memory to scan chains and configuring memory for scan dump. The use of latches and similar compact storage elements to form scannable memory can extend the testability of high-density memory circuits on complex integrated circuits operable at high clock speeds. A scannable memory architecture includes an input buffer with active low buffer latches, and an array of active high storage latches, operated in coordination to enable incorporation of the memory into scan chains for ATPG/TT and scan dump testing modes.