Abstract: Device and method of forming the device are disclosed. A semiconductor device includes a back-end-of-line dielectric (BEOL) with a plurality of IMD levels over a substrate processed with front-end-of-line components. The BEOL includes an upper IMD level and upper metal lines, with a buffer layer over the upper metal lines. The buffer layer improves adhesion of the upper IMD layer which covers the upper metal lines. Improving the adhesion of the upper IMD layer improves the reliability of the device.

Abstract: A technique which determines an optimum die layout on a semiconductor wafer is disclosed. The technique determines the optimum die layout with a significantly reduced number of calculations compared to conventional brute force techniques. This enables the generation of the optimum die layout in a much shorter period of time, reducing design turn-around time. The optimum layout is used to process a wafer which produces the optimum number of dies.

Abstract: A non-volatile memory cell structure and a method of fabricating the same. The method comprising the steps of: fabricating a portion of a floating gate from one or more first metal local interconnection layer (LIL) slit contacts deposited on a patterned dielectric layer; and fabricating a portion of a control gate from one or more second metal LIL slit contacts deposited on the patterned dielectric layer; wherein the first and second metal LIL slit contacts form a capacitive structure between the floating gate and the control gate.

Abstract: An electrically erasable programmable read only memory (EEPROM) cell structure and a method of fabricating the same. The EEPROM cell comprising a substrate comprising two shallow trench isolation (STI) structures separated by a substrate portion; an intermediate patterned layer formed on the substrate such that the patterned layer covers respective portions of each STI structure; a floating gate bridging between the STI structures such that the floating gate extends over the intermediate patterned layer; a dielectric layer formed over the floating gate; and a control gate formed over the dielectric layer.

Abstract: A non-volatile memory cell structure and a method of fabricating the same. The method comprising the steps of: fabricating a portion of a floating gate from one or more first metal local interconnection layer (LIL) slit contacts deposited on a patterned dielectric layer; and fabricating a portion of a control gate from one or more second metal LIL slit contacts deposited on the patterned dielectric layer; wherein the first and second metal LIL slit contacts form a capacitive structure between the floating gate and the control gate.

Abstract: An electrically erasable programmable read only memory (EEPROM) cell structure and a method of fabricating the same. The EEPROM cell comprising a substrate comprising two shallow trench isolation (STI) structures separated by a substrate portion; an intermediate patterned layer formed on the substrate such that the patterned layer covers respective portions of each STI structure; a floating gate bridging between the STI structures such that the floating gate extends over the intermediate patterned layer; a dielectric layer formed over the floating gate; and a control gate formed over the dielectric layer.

Abstract: A Metal-Insulator-Metal Capacitor and Method for Fabricating Metal-Insulator-Metal Capacitor Structures. The MIM (Metal insulator Metal) capacitor structure comprising a Capacitor Top Metal (CTM); a dielectric; and a Capacitor Bottom Metal (CBM); said CTM comprising an etch stop portion; a conductivity portion having a lower resistivity compared to the etch stop portion; and an interface portion of a different material from the conductivity portion; wherein the conductivity portion is sandwiched between the etch stop portion and the interface portion; and the interface portion interfaces the CTM with the dielectric.

Abstract: A system and method for measuring tool performance of a multi-path cluster semiconductor fabrication tool. The system comprises a status data unit for receiving up or down status data for each element of the tool for respective operational time periods; a performance value assignment unit for assigning a performance value to the tool for each time period based on the status data of the elements during said each time period; and an operational uptime unit for determining an operational uptime for a period covering the time periods of the tool based on multiplying the respective time periods with the corresponding assigned performance values.

Abstract: The present disclosure relates to a metal comb structure including a first comb which includes a first set of metal fingers each of the metal fingers being connected at one end thereof by a connecting member from which the metal fingers extend. The metal comb structure also includes a second comb which includes a first set of metal fingers inter-digitated with the metal fingers of the first comb, a first set of vias associated with the metal fingers of the second comb and a connecting member connected to the vias thereby connecting the metal fingers of the second comb. The vias extend from the metal fingers of the second comb such that the connecting member of the second comb is located outside a plane defined by the metal fingers of the first and second combs.

Abstract: A method and system for determining a predicted flash endurance Vt of a flash cell after N program/erase cycles. The method includes measuring a Vtp value and a Vte value of the flash cell after a cycle number in a range from 2000 to less than N/2 program/erase cycles; calculating a Vtp slope of a line starting from the measured Vtp value in a half logarithmic graph representation based on historical test data from flash cells of wafers having substantially the same process steps compared to the flash cell under investigation; calculating a Vte slope of a line starting from the measured Vte value in a half logarithmic graph representation based on the historical test data; and determining the Vtp and Vte values at 2 million program/erase cycles by extrapolating from the measured Vte and Vtp values.

Abstract: In a first aspect according to the invention there is provided a sensing system 100, suitable for sensing the stage of processing of a wafer 200, said sensing system 100 comprising receiving means 110 in the form of a first photosensitive device 110a and a second photosensitive device 110b, detector 120, a comparator 130 and a control system in the form of a programmable logic controller (PLC) 140. The first photosensitive device 110a receives light from the wafer 200, while the second photosensitive device 110b receives ambient light. The light received by the first photosensitive device 110a can be incident ambient light reflected off the surface of the wafer 200, refracted light radiating through the wafer 200, filtered light radiating through the wafer 200 or translucent light radiating through the wafer 200. It is further envisaged that the received light may be filtered through filters (not shown) before being received by the photosensitive devices 110a&b.

Abstract: A system and method for optimizing cleaning of a probe card including using the probe card to test the functionality of dies on a wafer, when a die fails the probe test, and the probe reports failure to contact the pads of the die, checking the resistance of the probe needles, and if the resistance of a probe needle is greater than a predetermined value triggering probe needle cleaning.

Abstract: A method for fabricating a Single Electron Transistor (SET). The method comprises forming a FinFET structure, forming an SET structure from the FinFET structure such that an active area of the SET structure is formed from a channel of the FinFET structure, whereby the active area is self-aligned with a source and a drain of the FinFET structure to form the SET structure.

Abstract: The present disclosure relates to a metal comb structure including a first comb which includes a first set of metal fingers each of the metal fingers being connected at one end thereof by a connecting member from which the metal fingers extend. The metal comb structure also includes a second comb which includes a first set of metal fingers inter-digitated with the metal fingers of the first comb, a first set of vias associated with the metal fingers of the second comb and a connecting member connected to the vias thereby connecting the metal fingers of the second comb. The vias extend from the metal fingers of the second comb such that the connecting member of the second comb is located outside a plane defined by the metal fingers of the first and second combs.

Abstract: A system for identifying systematic yield losses comprises a device configured to test produced products using a test sequence that produces yield data related to a wafer. The wafer is divided into multiple zones. Series of yield data may be collected and stored for each zone. A first data series R1 is the yield of a zone; a second data series R2 is a p consecutive element moving average of data series R1; and a third data series R3 is a p consecutive element moving standard deviation of data series R1. A device is configured to calculate a trigger point for each element of R1, wherein the trigger point is calculated as the respective R2 element less an adjusted respective R3 value. A notification may be provided to a user when the trigger point calculated for each element of R1 is greater than the respective element of R1.

Abstract: A method of determining the time to failure of parallel electro migration test structures is described. The method generally includes the steps of: measuring the resistance of the complete structure; calculating the resistance of the n individual parallel structures from the measured resistance; calculating the resistance of the complete structure after the failure of m individual parallel structures, for m=1 to n; and recording the time of failure for each m as the time when the resistance is approximately the value predicted for m fails.

Abstract: A method and system for determining a predicted flash endurance Vt of a flash cell after N program/erase cycles.

Abstract: A system and method for measuring tool performance of a multi-path cluster semiconductor fabrication tool. The system comprises a status data unit for receiving up or down status data for each element of the tool for respective operational time periods; a performance value assignment unit for assigning a performance value to the tool for each time period based on the status data of the elements during said each time period; and an operational uptime unit for determining an operational uptime for a period covering the time periods of the tool based on multiplying the respective time periods with the corresponding assigned performance values.

Abstract: A method of junction delineation of non-epitaxial wafers comprises the steps of preparing a sample of the wafer, staining the sample using a mixture of between one and three parts hydrofluoric acid to fifty parts nitric acid to twenty parts water, and scanning the sample with a scanning electron microscope.

Abstract: A waveguide liner for an analyzer magnet chamber having three interlocking pieces of graphite, the liner pieces having sufficient size to allow them to stand freely without being secured, said liner pieces providing case of interchange and replacement in a Kestrel analyzer magnet chamber.