Abstract: A CMP tool for polishing a semiconductor wafer is disclosed. The CMP tool includes a polishing head with a wafer carrier unit on which a wafer is mounted for polishing. The wafer carrier unit includes a support plate with a seal disposed on its sidewall. The seal improves sealing of the flexible membrane to the support plate. This improves reliability by avoiding slippage during the dechucking stage as well as wafer slippage during wafer loading stage, thereby avoiding wafer damage as well as non-uniform polishing.

Abstract: A method of TEM sample preparation from a circuit layer structure, the method comprising electron-beam assisted deposition of a first protective layer over a site of interest of the circuit layer structure; ion-beam assisted deposition of a second protective layer over the first protective layer; and ion-beam milling at the site of interest through the first and second protective layers.

Abstract: A thin Titanium underlayer 22 is included beneath a Titanium rich Titanium Nitride layer 28 in a metal line 20 on a silicon substrate to reduce stress voiding.

Abstract: A method for etching windows 40 in a semiconductor device 10 having a metal fuse 14 embedded therein is disclosed. The method is for allowing accurate fuse blowing, in particular laser fuse blowing. The method involves the controlled removal of layers having different phase diffraction characteristics. After treatment, the remaining area between the metal fuse 14 and the etched surface of the semiconductor has substantially uniform phase diffraction characteristics.

Abstract: In a wafer fabrication plant, the capacity management process 10 begins with identifying an initial capacity plan based on a demand plan (step 12). For each Product Group in the initial capacity plan a consumption sensitivity factor is defined (step 14). Next, a bottleneck capability variable is calculated (step 16). The capacity boundaries for each of the product groups are next determined (step 18). Thereafter, in the first of two branches, a determination of maximum wafer output is then performed for changing Product Group mixes to determine a maximum (step 20). The Product Group mix giving maximum wafer output is then determined for the fabrication plant (step 22). In the second branch, a determination of maximum profit is performed for changing Product Group mixes (step 24), then the Product Group mix giving maximum profit is determined for the fabrication plant (step 26).

Abstract: In a wafer fabrication plant, the capacity management process 10 begins with identifying an initial capacity plan based on a demand plan (step 12). For each Product Group in the initial capacity plan a consumption sensitivity factor is defined (step 14). Next, a bottleneck capability variable is calculated (step 16). The capacity boundaries for each of the product groups are next determined (step 18). Thereafter, in the first of two branches, a determination of maximum wafer output is then performed for changing Product Group mixes to determine a maximum (step 20). The Product Group mix giving maximum wafer output is then determined for the fabrication plant (step 22). In the second branch, a determination of maximum profit is performed for changing Product Group mixes (step 24), then the Product Group mix giving maximum profit is determined for the fabrication plant (step 26).

Abstract: A method of TEM sample preparation from a circuit layer structure, the method comprising electron-beam assisted deposition of a first protective layer over a site of interest of the circuit layer structure; ion-beam assisted deposition of a second protective layer over the first protective layer; and ion-beam milling at the site of interest through the first and second protective layers.

Abstract: A burn-in PCB comprising an adapter socket for receiving at least one program card; a plurality of test sockets for receiving test components; wherein one or more of the test sockets are electrically connected to the adapter socket by way of the printed circuit of the burn-in PCB; and wherein electrical connections for burn-in testing to respective test components received in said one or more test sockets on the burn-in PCB are at least in part formed by the printed circuit on said at least one program card received in the adapter socket.