Abstract: A central processor exercises on-off power control over a number of widely spaced loads and determines the status of the loads through a system which includes a transmitter-receiver terminal at each load and a common data bus connecting the central station to all of the transmitter-receivers. Each receiver has a unique address and the processor addresses one of the receivers by sending a message consisting of the receiver's address plus a command signal over the bus. A valid message consists of two sequential transmissions of the unit's address and the combination of command signals that accompany these addresses determines the function that is enabled at the receiver. All transmissions are serial and repeaters interposed in the bus restore signal levels and provide power to nearby terminals.