Abstract: This invention is about a method to make an MRAM element with small dimension, by making an MTJ as close as possible to the via, ideally aligning the MTJ and the via in a direction perpendicular to the wafer surface, for making the MRAM element dimension as small as possible. The invention provides a process scheme to flatten the interface of bottom electrode during film deposition, which ensures a good deposition of atomically smooth MTJ multilayer as close as possible to an associated via which otherwise might be atomically rough. The flattening scheme is first to deposit a thin amorphous conducting layer in the middle of BE deposition and immediately to bombard the amorphous layer by low energy ions to provide kinetic energy for surface atom diffusion to move from high point to low kinks. With such surface flattening scheme, not only the MRAM element can be made extremely small, but its device performance and magnetic stability can also be greatly improved.
Abstract: A planar STT-MRAM includes apparatus, made by a method of operating and a method of manufacturing a spin-torque magnetoresistive memory and a plurality of magnetoresistive memory element having a ferromagnetic recording layer forming a flux closure with a self-aligned ferromagnetic soft adjacent layer which has an electric field enhanced perpendicular anisotropy through an interface interaction with a dielectric functional layer. The energy switch barrier of the soft adjacent layer is reduced under an electric field along a perpendicular direction with a proper voltage on a digital line from a control circuitry; accordingly, the in-plane magnetization of the recording layer is readily reversible in a low spin-transfer switching current.
Type:
Grant
Filed:
December 27, 2015
Date of Patent:
May 30, 2017
Assignee:
T3Memory USA, Inc., a California US corporation