Patents Assigned to Taiwan Memory Company
  • Patent number: 8778760
    Abstract: A method of manufacturing a flash memory cell includes providing a substrate having a first dielectric layer formed thereon, forming a control gate on the first dielectric layer, forming an oxide-nitride-oxide (ONO) spacer on sidewalls of the control gate, forming a second dielectric layer on the substrate at two sides of the ONO spacer, and forming a floating gate at outer sides of the ONO spacer on the second dielectric layer, respectively.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: July 15, 2014
    Assignee: Taiwan Memory Company
    Inventors: Yung-Chang Lin, Nan-Ray Wu, Le-Tien Jung
  • Publication number: 20140106526
    Abstract: A method of manufacturing a flash memory cell includes providing a substrate having a first dielectric layer formed thereon, forming a control gate on the first dielectric layer, forming an oxide-nitride-oxide (ONO) spacer on sidewalls of the control gate, forming a second dielectric layer on the substrate at two sides of the ONO spacer, and forming a floating gate at outer sides of the ONO spacer on the second dielectric layer, respectively.
    Type: Application
    Filed: December 23, 2013
    Publication date: April 17, 2014
    Applicant: Taiwan Memory Company
    Inventors: Yung-Chang Lin, Nan-Ray Wu, Le-Tien Jung
  • Patent number: 8664062
    Abstract: A method of manufacturing a flash memory cell includes providing a substrate having a first dielectric layer formed thereon, forming a control gate on the first dielectric layer, forming an oxide-nitride-oxide (ONO) spacer on sidewalls of the control gate, forming a second dielectric layer on the substrate at two sides of the ONO spacer, and forming a floating gate at outer sides of the ONO spacer on the second dielectric layer, respectively.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: March 4, 2014
    Assignee: Taiwan Memory Company
    Inventors: Yung-Chang Lin, Nan-Ray Wu, Le-Tien Jung
  • Patent number: 8431485
    Abstract: A manufacturing method for a buried circuit structure includes providing a substrate having at least a trench formed therein, forming a firs conductive layer on the substrate blanketly, forming a patterned photoresist having a surface lower than an opening of the trench in the trench, removing the first conductive layer not covered by the patterned photoresist to form a second conductive layer having a top lower than an opening of the trench in the trench, removing the patterned photoresist, performing a dry etching process to remove the second conductive layer from the bottom of the trench to form a third conductive layer on the sidewalls of the trench, performing a selective metal chemical vapor deposition to form a metal layer having a surface lower than a surface of the substrate, and forming a protecting layer filling the trench on the metal layer.
    Type: Grant
    Filed: April 9, 2012
    Date of Patent: April 30, 2013
    Assignee: Taiwan Memory Company
    Inventors: Le-Tien Jung, Tai-Sheng Feng
  • Patent number: 8183146
    Abstract: A manufacturing method for a buried circuit structure includes providing a substrate having at least a trench therein, forming a conductive layer having a top lower than an opening of the trench in the trench, performing a selective metal chemical vapor deposition (CVD) to form a metal layer having a top lower than the substrate in the trench, and forming a protecting layer filling the trench on the metal layer.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: May 22, 2012
    Assignee: Taiwan Memory Company
    Inventors: Tai-Sheng Feng, Le-Tien Jung