Patents Assigned to Taiwan Memory Corporation
  • Patent number: 8748961
    Abstract: The embodiment provides a buried bit line process and scheme. The buried bit line is disposed in a trench formed in a substrate. The buried bit line includes a diffusion region formed in a portion of the substrate adjacent the trench. A blocking layer is formed on a portion sidewall of the trench. A conductive plug is formed in the trench, covering sidewalls of the diffusion region and the blocking layer.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: June 10, 2014
    Assignee: Taiwan Memory Corporation
    Inventors: Le-Tien Jung, Yung-Chang Lin
  • Patent number: 8143136
    Abstract: A method for fabricating a crown-shaped capacitor includes providing a first dielectric layer with a protective pillar formed thereover, including a first conductive layer, a protective layer, and a mask layer. A second conductive layer is formed over a sidewall of the protective pillar. A first capacitance layer and a third conductive layer are formed over the first dielectric layer. A sacrificial layer is formed over the third conductive layer. The sacrificial layer, the third conductive layer, the first capacitance layer, the second conductive layer, and the mask layer above the protective layer are partially removed. The second conductive layer and the third conductive are removed to form a recess adjacent to the first capacitance layer. The protective layer is removed and an opening is formed to expose the first and second conductive layers. A second capacitance layer and a fourth conductive layer are formed in the opening. The sacrificial layer is removed to expose the third conductive layer.
    Type: Grant
    Filed: December 28, 2010
    Date of Patent: March 27, 2012
    Assignee: Taiwan Memory Corporation
    Inventor: Chao-Hsi Chung
  • Publication number: 20110101435
    Abstract: The embodiment provides a buried bit line process and scheme. The buried bit line is disposed in a trench formed in a substrate. The buried bit line includes a diffusion region formed in a portion of the substrate adjacent the trench. A blocking layer is formed on a portion sidewall of the trench. A conductive plug is formed in the trench, covering sidewalls of the diffusion region and the blocking layer.
    Type: Application
    Filed: November 5, 2010
    Publication date: May 5, 2011
    Applicant: TAIWAN MEMORY CORPORATION
    Inventors: Le-Tien JUNG, Yung-Chang LIN