Abstract: A memory device comprises a tracking control circuit for controlling the write operation or the read operation of the memory device. The tracking control circuit comprises a plurality of tracking cells, wherein the timing characteristics of the tracking cells emulate the timing characteristics of a bit cell during a write operation or a read operation of the memory device. The memory device further comprises at least two reference word lines for configuring the number of tracking cells of the tracking control circuit; and a selection circuit configured to activate one or more of the at least two reference word lines.

Abstract: A method for manufacturing a pellicle includes: providing a supporting substrate; forming an oxide layer over the supporting substrate; forming a metal layer over the oxide layer; forming a graphene layer over the metal layer; and removing at least a portion of the supporting substrate and the oxide layer. An associated method includes: providing a supporting substrate; forming a first silicon carbide (SiC) layer or a diamond layer over the supporting substrate; forming a graphene layer over the SiC layer or the diamond layer; and removing at least a portion of the supporting substrate and the first silicon carbide (SiC) layer or the diamond layer; wherein the pellicle is at least partially transparent to extreme ultraviolet (EUV) radiation. An associated pellicle is also disclosed.

Abstract: An integrated circuit device includes a semiconductor substrate, and a semiconductor strip extending into the semiconductor substrate. A first and a second dielectric region are on opposite sides of, and in contact with, the semiconductor strip. Each of the first dielectric region and the second dielectric region includes a first portion level with the semiconductor strip, and a second portion lower than the semiconductor strip. The second portion further includes a portion overlapped by the semiconductor strip.

Abstract: A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region.

Abstract: An embodiment is a method including forming a first gate over a substrate, the first gate having first gate spacers on opposing sidewalls, forming a first hard mask layer over the first gate, forming a second hard mask layer over the first hard mask layer, the second hard mask layer having a different material composition than the first hard mask layer, forming a first dielectric layer adjacent and over the first gate, etching a first opening through the first dielectric layer to expose a portion of the substrate, at least a portion of the second hard mask layer being exposed in the first opening, filling the first opening with a conductive material, and removing the second hard mask layer and the portions of the conductive material and first dielectric layer above the first hard mask layer to form a first conductive contact in the remaining first dielectric layer.

Abstract: A microelectromechanical system (MEMS) device includes a substrate and a movable element at least partially suspended above the substrate and having at least one degree of freedom. The MEMS device further includes a protrusion extending from the substrate and configured to contact the movable element when the movable element moves in the at least one degree of freedom, wherein the protrusion comprises a surface having a water contact angle of higher than about 15° measured in air.

Abstract: A semiconductor structure includes a substrate including a first surface, a second surface opposite to the first surface and a recess extending from the first surface towards the second surface, a first die at least partially disposed within the recess and including a first die substrate and a first bonding member disposed over the first die substrate, a second die disposed over the first die and including a second die substrate and a second bonding member disposed a second die substrate and the second die substrate, a redistribution layer (RDL) disposed over the second die, and a conductive bump disposed over the RDL, wherein the first bonding member is disposed opposite to and is bonded with the second bonding member.

Abstract: A bio-chip package comprises a substrate a first layer over the substrate comprising an image sensor. The bio-chip package also comprises a second layer over the first layer. The second layer comprises a waveguide system a grating coupler. The bio-chip package also comprises a third layer arranged to accommodate a fluid between a first-third layer portion and a second-third layer portion, and to allow the fluid to pass from a first side of the third layer to a second side of the third layer. The third layer comprises a material having a predetermined transparency with respect to a wavelength of a received source light, the waveguide system is configured to direct the received source light to the grating coupler, and the image sensor is configured to determine a change in the wavelength of the source light caused by a coupling between the source light and the fluid.

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a System on Chip (SoC) die; an integrated passive device (IPD); and a first switch, coupled between the SoC die and the IPD; wherein the IPD and the SoC die are disposed in different wafers and bonded together, and the first switch is controlled to disconnect the IPD from the SoC die when the IPD is under a test; and the first switch is controlled to connect the IPD with the SoC die when the IPD is not under the test. A test system for testing an IPD of a semiconductor device and an associated method are also disclosed.

Abstract: A method for forming a protecting layer includes determining an expected concentration of metal ions in a dielectric layer. The method also includes determining a thickness of the protecting layer based on the expected concentration of metal ions. The method also includes forming the protecting layer at the determined thickness and in contact with the dielectric layer. The protecting layer can include at least one of silicon doped nitride, carbon nitride, silicon nitride, or silicon carbon.

Abstract: A micro-device includes a substrate with a cavity. The cavity is covered with a porous layer that is permeable to vapor hydrofluoric acid (HF) etchant. The micro-device comprises a Microelectromechanical Systems (MEMS) device with a component that is moveable in operational use of the MEMS device. The component is arranged within the cavity.

Abstract: A system and method for forming an underbump metallization (UBM) is presented. A preferred embodiment includes a raised UBM which extends through a passivation layer so as to make contact with a contact pad while retaining enough of the passivation layer between the contact pad and the UBM to adequately handle the peeling and shear stress that results from CTE mismatch and subsequent thermal processing. The UBM contact is preferably formed in either an octagonal ring shape or an array of contacts.

Abstract: An integrated circuit structure includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate, wherein the isolation regions have opposite sidewalls facing each other. A fin structure includes a silicon fin higher than top surfaces of the isolation regions, a germanium-containing semiconductor region overlapped by the silicon fin, silicon oxide regions on opposite sides of the germanium-containing semiconductor region, and a germanium-containing semiconductor layer between and in contact with the silicon fin and one of the silicon oxide regions.

Abstract: A system and method for forming photoresists over semiconductor substrates is provided. An embodiment comprises a photoresist with a concentration gradient. The concentration gradient may be formed by using a series of dry film photoresists, wherein each separate dry film photoresist has a different concentration. The separate dry film photoresists may be formed separately and then placed onto the semiconductor substrate before being patterned. Once patterned, openings through the photoresist may have a tapered sidewall, allowing for a better coverage of the seed layer and a more uniform process to form conductive materials through the photoresist.

Abstract: An energy harvesting device comprises a semiconductor device, and a first magnet core. The semiconductor device, disposed in a housing, includes planar inductors. The first magnet core, having a first surface over the planar inductors, is configured to move with respect to the semiconductor device in a first direction that reduces a first vertical distance between the plane and the first surface.

Abstract: Semiconductor devices, image sensors, and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a high dielectric constant (k) insulating material disposed over a workpiece, the high k insulating material having a dielectric constant of greater than about 3.9. A barrier layer is disposed over the high k insulating material. A buffer oxide layer including a porous oxide film is disposed between the high k insulating material and the barrier layer. The porous oxide film has a first porosity, and the barrier layer or the high k insulating material has a second porosity. The first porosity is greater than the second porosity.

Abstract: Packages structure and methods of forming them are discussed. A structure includes a first die, a first encapsulant at least laterally encapsulating the first die, and a redistribution structure on the first die and the first encapsulant. The second die is attached by an external electrical connector to the redistribution structure. The second die is on an opposite side of the redistribution structure from the first die. A second encapsulant is on the redistribution structure and at least laterally encapsulates the second die. The second encapsulant has a surface distal from the redistribution structure. A conductive feature extends from the redistribution structure through the second encapsulant to the surface of the second encapsulant. A conductive pillar is on the conductive feature, and the conductive pillar protrudes from the surface of the second encapsulant.

Abstract: Present disclosure provides a FinFET structure, including a plurality of fins, a gate, and a first dopant layer. The gate is disposed substantially orthogonal over the plurality of fins, covering a portion of a top surface and a portion of sidewalls of the plurality of fins. The first dopant layer covers the top surface and the sidewalls of a junction portion of a first fin, configured to provide dopants of a first conductive type to the junction portion of the first fin. The junction portion is adjacent to the gate.

Abstract: Embodiments relate to packages and methods of forming packages. A package includes a package substrate, a first device die, first electrical connectors, an encapsulant, a redistribution structure, and a second device die. The first device die is attached to a side of the package substrate, and the first electrical connectors are mechanically and electrically coupled to the side of the package substrate. The encapsulant at least laterally encapsulates the first electrical connectors and the first device die. The redistribution structure is on the encapsulant and the first electrical connectors. The redistribution structure is directly coupled to the first electrical connectors. The first device die is disposed between the redistribution structure and the package substrate. The second device die is attached to the redistribution structure by second electrical connectors, and the second electrical connectors are directly coupled to the redistribution structure.

Abstract: A method of designing an integrated circuit, that includes receiving a first list corresponding to at least one circuit component in a layout, generating a condensed layout from the layout and performing an electrostatic discharge (ESD) check of the condensed layout. The condensed layout is generated by a processor. The ESD check is configured to verify compliance with one or more ESD design rules. The condensed layout includes at least one circuit component. The at least one circuit component includes an ESD circuit and an associated ESD current path.