Abstract: A method includes forming a gate stack and an interlayer dielectric (ILD) over a substrate, wherein the interlayer dielectric is adjacent to the gate stack; forming an inhibitor covering the interlayer dielectric such that the gate stack is exposed from the inhibitor; performing a deposition process to form a conductive layer over the gate stack until the conductive layer starts to form on the inhibitor, in which the deposition process has a deposition selectivity for the gate stack with respect to the inhibitor; and performing an etching process to remove a portion of the conductive layer over the inhibitor.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate stack over a substrate and an insulating capping layer over the gate stack. The semiconductor device structure also includes a source/drain contact structure adjacent to the gate stack and having an upper surface that is substantially level with the upper surface of the insulating capping layer. The semiconductor device structure also includes a first via structure passing through the insulating capping layer and electrically connected to the gate stack, and a second via structure above and electrically connected to the source/drain contact structure. The first via structure and the second via structure have different vertical heights.

Abstract: A semiconductor furnace suitable for chemical vapor deposition processing of wafers. The furnace includes a thermal reaction chamber having a top, a bottom, a sidewall, and an internal cavity for removably holding a batch of vertically stacked wafers. A heating system is provided that includes a plurality of heaters arranged and operative to heat the chamber. The heating system includes at least one top heater; at least one bottom heater, and a plurality of sidewall heaters spaced along the height of the reaction chamber to control temperature variations within in the chamber and promote uniform film deposit thickness on the wafers.

Abstract: A system and method provides an improved source-coupling ratio in flash memories. In one embodiment, a flash memory cell system with high source-coupling ratio includes at least a conventional floating gate device having a floating gate, a drain and a source. The floating gate is formed over a first junction for charging the floating gate by electron injection from the source to the floating gate and at least a first dielectric is layered on top of the floating gate to form a second junction. At least a first polycrystalline silicon is layered on top of the first dielectric, the first polycrystalline silicon electrically connected to the source. Electron tunneling provided through the second junction to the floating gate charges the floating gate, thereby increasing the source-coupling ratio of the floating gate and increasing the efficiency of storing electrical charge.

Abstract: The present invention provides a method for fabricating a bottom electrode of a dynamic random access memory (DRAM) capacitor. First, a first sacrificial layer, an intermediate layer and a second sacrificial layer are sequentially formed on a substrate. Then, an aperture is formed on the first sacrificial layer, the intermediate layer and the second sacrificial layer. An annular groove is then formed in the inner circumferential surface of the aperture by removing a fixed depth of the intermediate layer. After that, the aperture and the annular groove are filled with a first amorphous silicon layer, a second amorphous silicon layer and a third amorphous silicon layer. The second amorphous silicon layer has a lower impurity concentration than those of the first amorphous silicon layer and the third amorphous silicon layer. The first amorphous silicon layer and the second amorphous silicon layer both fill into the annular groove and form an annular ring.